116 lines
4.1 KiB
C++
116 lines
4.1 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_REGISTERS_HH__
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#define __ARCH_ARM_REGISTERS_HH__
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#include "arch/arm/intregs.hh"
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#include "arch/arm/max_inst_regs.hh"
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#include "arch/arm/miscregs.hh"
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namespace ArmISA {
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// For a predicated instruction, we need all the
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// destination registers to also be sources
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const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
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ArmISAInst::MaxInstSrcRegs;
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using ArmISAInst::MaxInstDestRegs;
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typedef uint16_t RegIndex;
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typedef uint64_t IntReg;
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// floating point register file entry type
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typedef uint32_t FloatRegBits;
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typedef float FloatReg;
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// cop-0/cop-1 system control register
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typedef uint64_t MiscReg;
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// Constants Related to the number of registers
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const int NumIntArchRegs = NUM_ARCH_INTREGS;
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// The number of single precision floating point registers
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const int NumFloatArchRegs = 64;
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const int NumFloatSpecialRegs = 8;
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const int NumIntRegs = NUM_INTREGS;
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const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
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const int NumMiscRegs = NUM_MISCREGS;
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const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
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// semantically meaningful register indices
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const int ReturnValueReg = 0;
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const int ReturnValueReg1 = 1;
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const int ReturnValueReg2 = 2;
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const int NumArgumentRegs = 4;
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const int ArgumentReg0 = 0;
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const int ArgumentReg1 = 1;
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const int ArgumentReg2 = 2;
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const int ArgumentReg3 = 3;
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const int FramePointerReg = 11;
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const int StackPointerReg = INTREG_SP;
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const int ReturnAddressReg = INTREG_LR;
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const int PCReg = INTREG_PC;
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const int ZeroReg = INTREG_ZERO;
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const int SyscallNumReg = ReturnValueReg;
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const int SyscallPseudoReturnReg = ReturnValueReg;
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const int SyscallSuccessReg = ReturnValueReg;
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// These help enumerate all the registers for dependence tracking.
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const int FP_Base_DepTag = NumIntRegs * (MODE_MAXMODE + 1);
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const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
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const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
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typedef union {
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IntReg intreg;
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FloatReg fpreg;
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MiscReg ctrlreg;
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} AnyReg;
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} // namespace ArmISA
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#endif
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