96 lines
3.3 KiB
C++
96 lines
3.3 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Steve Reinhardt
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* Stephen Hines
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*/
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#ifndef __ARCH_ARM_LOCKED_MEM_HH__
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#define __ARCH_ARM_LOCKED_MEM_HH__
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/**
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* @file
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*
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* ISA-specific helper functions for locked memory accesses.
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*/
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#include "arch/arm/miscregs.hh"
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#include "mem/request.hh"
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namespace ArmISA
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{
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template <class XC>
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inline void
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handleLockedRead(XC *xc, Request *req)
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{
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xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
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xc->setMiscReg(MISCREG_LOCKFLAG, true);
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}
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template <class XC>
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inline bool
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handleLockedWrite(XC *xc, Request *req)
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{
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if (req->isSwap())
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return true;
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// Verify that the lock flag is still set and the address
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// is correct
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bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
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Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
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if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
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// Lock flag not set or addr mismatch in CPU;
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// don't even bother sending to memory system
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req->setExtraData(0);
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xc->setMiscReg(MISCREG_LOCKFLAG, false);
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// the rest of this code is not architectural;
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// it's just a debugging aid to help detect
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// livelock by warning on long sequences of failed
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// store conditionals
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int stCondFailures = xc->readStCondFailures();
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stCondFailures++;
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xc->setStCondFailures(stCondFailures);
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if (stCondFailures % 100000 == 0) {
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warn("context %d: %d consecutive "
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"store conditional failures\n",
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xc->contextId(), stCondFailures);
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}
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// store conditional failed already, so don't issue it to mem
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return false;
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}
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return true;
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}
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} // namespace ArmISA
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#endif
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