251 lines
8.1 KiB
C++
251 lines
8.1 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Gabe Black
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*/
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#include "arch/arm/faults.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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namespace ArmISA
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{
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template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
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{"reset", 0x00, MODE_SVC, 0, 0, true, true};
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template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
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{"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
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template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
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{"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
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template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
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{"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
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template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
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{"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
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template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
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{"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
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template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
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{"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
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template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
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{"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
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template<> ArmFault::FaultVals ArmFaultVals<ReExec>::vals =
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{"ReExec Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
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Addr
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ArmFault::getVector(ThreadContext *tc)
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{
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// ARM ARM B1-3
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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// panic if SCTLR.VE because I have no idea what to do with vectored
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// interrupts
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assert(!sctlr.ve);
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if (!sctlr.v)
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return offset();
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return offset() + HighVecs;
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}
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#if FULL_SYSTEM
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void
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ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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// ARM ARM B1.6.3
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FaultBase::invoke(tc);
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countStat()++;
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
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tc->readIntReg(INTREG_CONDCODES);
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Addr curPc M5_VAR_USED = tc->pcState().pc();
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ITSTATE it = tc->pcState().itstate();
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saved_cpsr.it2 = it.top6;
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saved_cpsr.it1 = it.bottom2;
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cpsr.mode = nextMode();
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cpsr.it1 = cpsr.it2 = 0;
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cpsr.j = 0;
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cpsr.t = sctlr.te;
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cpsr.a = cpsr.a | abortDisable();
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cpsr.f = cpsr.f | fiqDisable();
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cpsr.i = 1;
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cpsr.e = sctlr.ee;
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tc->setMiscReg(MISCREG_CPSR, cpsr);
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tc->setIntReg(INTREG_LR, curPc +
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(saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
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switch (nextMode()) {
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case MODE_FIQ:
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tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
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break;
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case MODE_IRQ:
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tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
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break;
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case MODE_SVC:
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tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
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break;
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case MODE_UNDEFINED:
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tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
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break;
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case MODE_ABORT:
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tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
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break;
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default:
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panic("unknown Mode\n");
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}
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Addr newPc = getVector(tc);
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DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
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name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
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PCState pc(newPc);
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pc.thumb(cpsr.t);
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pc.nextThumb(pc.thumb());
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pc.jazelle(cpsr.j);
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pc.nextJazelle(pc.jazelle());
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tc->pcState(pc);
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}
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void
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Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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tc->getCpuPtr()->clearInterrupts();
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tc->clearArchRegs();
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ArmFault::invoke(tc, inst);
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}
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#else
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void
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UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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// If the mnemonic isn't defined this has to be an unknown instruction.
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assert(unknown || mnemonic != NULL);
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if (disabled) {
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panic("Attempted to execute disabled instruction "
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"'%s' (inst 0x%08x)", mnemonic, machInst);
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} else if (unknown) {
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panic("Attempted to execute unknown instruction (inst 0x%08x)",
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machInst);
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} else {
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panic("Attempted to execute unimplemented instruction "
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"'%s' (inst 0x%08x)", mnemonic, machInst);
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}
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}
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void
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SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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// As of now, there isn't a 32 bit thumb version of this instruction.
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assert(!machInst.bigThumb);
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uint32_t callNum;
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callNum = tc->readIntReg(INTREG_R7);
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tc->syscall(callNum);
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// Advance the PC since that won't happen automatically.
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PCState pc = tc->pcState();
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assert(inst);
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inst->advancePC(pc);
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tc->pcState(pc);
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}
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#endif // FULL_SYSTEM
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template<class T>
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void
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AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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ArmFaultVals<T>::invoke(tc, inst);
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FSR fsr = 0;
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fsr.fsLow = bits(status, 3, 0);
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fsr.fsHigh = bits(status, 4);
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fsr.domain = domain;
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fsr.wnr = (write ? 1 : 0);
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fsr.ext = 0;
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tc->setMiscReg(T::FsrIndex, fsr);
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tc->setMiscReg(T::FarIndex, faultAddr);
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}
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void
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FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
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DPRINTF(Faults, "Invoking FlushPipe Fault\n");
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// Set the PC to the next instruction of the faulting instruction.
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// Net effect is simply squashing all instructions behind and
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// start refetching from the next instruction.
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PCState pc = tc->pcState();
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assert(inst);
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inst->advancePC(pc);
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tc->pcState(pc);
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}
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void
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ReExec::invoke(ThreadContext *tc, StaticInstPtr inst) {
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DPRINTF(Faults, "Invoking ReExec Fault\n");
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// Set the PC to then the faulting instruction.
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// Net effect is simply squashing all instructions including this
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// instruction and refetching/rexecuting current instruction
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PCState pc = tc->pcState();
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tc->pcState(pc);
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}
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template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
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StaticInstPtr inst);
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template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
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StaticInstPtr inst);
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// return via SUBS pc, lr, xxx; rfe, movs, ldm
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} // namespace ArmISA
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