gem5/tests
Andreas Hansson f00cba34eb Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.

There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.
2012-07-12 12:56:13 -04:00
..
configs Mem: Make SimpleMemory single ported 2012-07-12 12:56:13 -04:00
long Regression: update ruby.stats file 2012-07-12 08:39:20 -05:00
quick Regression: update ruby.stats file 2012-07-12 08:39:20 -05:00
test-progs/hello X86: Add a 32 bit hello world test binary. 2012-05-27 19:01:09 -07:00
diff-out tests: fix diff-out script for op/inst stat changes. 2012-02-12 18:35:59 -06:00
halt.sh Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon. 2006-07-21 15:56:35 -04:00
run.py SE/FS: Make both SE and FS tests available all the time. 2012-01-28 07:24:45 -08:00
SConscript Regression: Add ANSI colours to highlight test status 2012-04-14 05:44:27 -04:00