5a9a743cfc
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
189 lines
8 KiB
Python
189 lines
8 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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def define_options(parser):
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# ruby network options
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parser.add_option("--topology", type="string", default="Crossbar",
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help="check src/mem/ruby/network/topologies for complete set")
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parser.add_option("--mesh-rows", type="int", default=1,
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help="the number of rows in the mesh topology")
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parser.add_option("--garnet-network", type="string", default=None,
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help="'fixed'|'flexible'")
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parser.add_option("--network-fault-model", action="store_true", default=False,
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help="enable network fault model: see src/mem/ruby/network/fault_model/")
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# ruby mapping options
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parser.add_option("--numa-high-bit", type="int", default=0,
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help="high order address bit to use for numa mapping. " \
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"0 = highest bit, not specified = lowest bit")
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# ruby sparse memory options
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parser.add_option("--use-map", action="store_true", default=False)
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parser.add_option("--map-levels", type="int", default=4)
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parser.add_option("--recycle-latency", type="int", default=10,
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help="Recycle latency for ruby controller input buffers")
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parser.add_option("--random_seed", type="int", default=1234,
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help="Used for seeding the random number generator")
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parser.add_option("--ruby_stats", type="string", default="ruby.stats")
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protocol = buildEnv['PROTOCOL']
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exec "import %s" % protocol
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eval("%s.define_options(parser)" % protocol)
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def create_system(options, system, piobus = None, dma_devices = []):
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system.ruby = RubySystem(clock = options.clock,
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stats_filename = options.ruby_stats,
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no_mem_vec = options.use_map)
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ruby = system.ruby
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protocol = buildEnv['PROTOCOL']
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exec "import %s" % protocol
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try:
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(cpu_sequencers, dir_cntrls, all_cntrls) = \
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eval("%s.create_system(options, system, piobus, \
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dma_devices, ruby)" \
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% protocol)
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except:
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print "Error: could not create sytem for ruby protocol %s" % protocol
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raise
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# Create a port proxy for connecting the system port. This is
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# independent of the protocol and kept in the protocol-agnostic
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# part (i.e. here).
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sys_port_proxy = RubyPortProxy(version = 0,
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physMemPort = system.physmem.port,
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physmem = system.physmem,
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ruby_system = ruby)
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# Give the system port proxy a SimObject parent without creating a
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# full-fledged controller
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system.sys_port_proxy = sys_port_proxy
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# Connect the system port for loading of binaries etc
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system.system_port = system.sys_port_proxy.slave
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#
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# Set the network classes based on the command line options
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#
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if options.garnet_network == "fixed":
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class NetworkClass(GarnetNetwork_d): pass
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class IntLinkClass(GarnetIntLink_d): pass
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class ExtLinkClass(GarnetExtLink_d): pass
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class RouterClass(GarnetRouter_d): pass
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elif options.garnet_network == "flexible":
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class NetworkClass(GarnetNetwork): pass
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class IntLinkClass(GarnetIntLink): pass
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class ExtLinkClass(GarnetExtLink): pass
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class RouterClass(GarnetRouter): pass
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else:
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class NetworkClass(SimpleNetwork): pass
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class IntLinkClass(SimpleIntLink): pass
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class ExtLinkClass(SimpleExtLink): pass
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class RouterClass(BasicRouter): pass
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#
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# Important: the topology must be created before the network and after the
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# controllers.
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#
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exec "import %s" % options.topology
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try:
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net_topology = eval("%s.makeTopology(all_cntrls, options, \
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IntLinkClass, ExtLinkClass, \
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RouterClass)" \
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% options.topology)
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except:
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print "Error: could not create topology %s" % options.topology
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raise
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if options.network_fault_model:
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assert(options.garnet_network == "fixed")
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fault_model = FaultModel()
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network = NetworkClass(ruby_system = ruby, topology = net_topology,\
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enable_fault_model=True, fault_model = fault_model)
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else:
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network = NetworkClass(ruby_system = ruby, topology = net_topology)
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#
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# Loop through the directory controlers.
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# Determine the total memory size of the ruby system and verify it is equal
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# to physmem. However, if Ruby memory is using sparse memory in SE
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# mode, then the system should not back-up the memory state with
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# the Memory Vector and thus the memory size bytes should stay at 0.
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# Also set the numa bits to the appropriate values.
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#
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total_mem_size = MemorySize('0B')
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dir_bits = int(math.log(options.num_dirs, 2))
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if options.numa_high_bit:
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numa_bit = options.numa_high_bit
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else:
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# if not specified, use the lowest bits above the block offest
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if dir_bits > 0:
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# add 5 because bits 0-5 are the block offset
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numa_bit = dir_bits + 5
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else:
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numa_bit = 6
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for dir_cntrl in dir_cntrls:
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total_mem_size.value += dir_cntrl.directory.size.value
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dir_cntrl.directory.numa_high_bit = numa_bit
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physmem_size = long(system.physmem.range.second) - \
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long(system.physmem.range.first) + 1
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assert(total_mem_size.value == physmem_size)
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ruby_profiler = RubyProfiler(ruby_system = ruby,
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num_of_sequencers = len(cpu_sequencers))
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ruby.network = network
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ruby.profiler = ruby_profiler
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ruby.mem_size = total_mem_size
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ruby._cpu_ruby_ports = cpu_sequencers
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ruby.random_seed = options.random_seed
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