78275c9d2f
The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).
This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.
PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.
The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.
Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:
* Configurable configuration space decoding. The number of bits
dedicated to a device is a prameter, making it possible to support
both CAM, ECAM, and legacy mappings.
* Basic interrupt mapping using the interruptLine value from a
device's configuration space. This behavior is the same as in the
old implementation. More advanced controllers can override the
interrupt mapping method to dynamically assign host interrupts to
PCI devices.
* Simple (base + addr) remapping from the PCI bus's address space to
physical addresses for PIO, memory, and DMA.
657 lines
25 KiB
Python
657 lines
25 KiB
Python
# Copyright (c) 2010-2012, 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
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# Copyright (c) 2006-2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Kevin Lim
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from m5.objects import *
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from Benchmarks import *
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from m5.util import *
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import PlatformConfig
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# Populate to reflect supported os types per target ISA
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os_types = { 'alpha' : [ 'linux' ],
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'mips' : [ 'linux' ],
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'sparc' : [ 'linux' ],
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'x86' : [ 'linux' ],
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'arm' : [ 'linux',
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'android-gingerbread',
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'android-ics',
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'android-jellybean',
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'android-kitkat' ],
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}
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class CowIdeDisk(IdeDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True),
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read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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class MemBus(SystemXBar):
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badaddr_responder = BadAddr()
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default = Self.badaddr_responder.pio
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def fillInCmdline(mdesc, template, **kwargs):
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kwargs.setdefault('disk', mdesc.disk())
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kwargs.setdefault('rootdev', mdesc.rootdev())
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kwargs.setdefault('mem', mdesc.mem())
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kwargs.setdefault('script', mdesc.script())
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return template % kwargs
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def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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self = LinuxAlphaSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.tsunami = BaseTsunami()
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# Create the io bus to connect all device ports
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self.iobus = IOXBar()
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self.tsunami.attachIO(self.iobus)
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self.tsunami.ide.pio = self.iobus.master
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self.tsunami.ethernet.pio = self.iobus.master
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if ruby:
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# Store the dma devices for later connection to dma ruby ports.
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# Append an underscore to dma_ports to avoid the SimObjectVector check.
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self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
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else:
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self.membus = MemBus()
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# By default the bridge responds to all addresses above the I/O
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# base address (including the PCI config space)
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IO_address_space_base = 0x80000000000
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self.bridge = Bridge(delay='50ns',
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ranges = [AddrRange(IO_address_space_base, Addr.max)])
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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self.tsunami.ide.dma = self.iobus.slave
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self.tsunami.ethernet.dma = self.iobus.slave
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self.system_port = self.membus.slave
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self.mem_ranges = [AddrRange(mdesc.mem())]
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(mdesc.disk())
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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self.intrctrl = IntrControl()
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self.mem_mode = mem_mode
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self.terminal = Terminal()
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self.kernel = binary('vmlinux')
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self.pal = binary('ts_osfpal')
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self.console = binary('console')
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if not cmdline:
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cmdline = 'root=/dev/hda1 console=ttyS0'
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self.boot_osflags = fillInCmdline(mdesc, cmdline)
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return self
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def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
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# Constants from iob.cc and uart8250.cc
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iob_man_addr = 0x9800000000
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uart_pio_size = 8
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class CowMmDisk(MmDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True),
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read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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self = SparcSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = IOXBar()
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self.membus = MemBus()
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self.bridge = Bridge(delay='50ns')
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self.t1000 = T1000()
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self.t1000.attachOnChipIO(self.membus)
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self.t1000.attachIO(self.iobus)
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self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
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AddrRange(Addr('2GB'), size ='256MB')]
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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self.rom.port = self.membus.master
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self.nvram.port = self.membus.master
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self.hypervisor_desc.port = self.membus.master
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self.partition_desc.port = self.membus.master
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self.intrctrl = IntrControl()
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self.disk0 = CowMmDisk()
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self.disk0.childImage(disk('disk.s10hw2'))
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self.disk0.pio = self.iobus.master
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# The puart0 and hvuart are placed on the IO bus, so create ranges
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# for them. The remaining IO range is rather fragmented, so poke
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# holes for the iob and partition descriptors etc.
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self.bridge.ranges = \
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[
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AddrRange(self.t1000.puart0.pio_addr,
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self.t1000.puart0.pio_addr + uart_pio_size - 1),
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AddrRange(self.disk0.pio_addr,
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self.t1000.fake_jbi.pio_addr +
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self.t1000.fake_jbi.pio_size - 1),
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AddrRange(self.t1000.fake_clk.pio_addr,
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iob_man_addr - 1),
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AddrRange(self.t1000.fake_l2_1.pio_addr,
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self.t1000.fake_ssi.pio_addr +
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self.t1000.fake_ssi.pio_size - 1),
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AddrRange(self.t1000.hvuart.pio_addr,
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self.t1000.hvuart.pio_addr + uart_pio_size - 1)
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]
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self.reset_bin = binary('reset_new.bin')
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self.hypervisor_bin = binary('q_new.bin')
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self.openboot_bin = binary('openboot_new.bin')
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self.nvram_bin = binary('nvram1')
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self.hypervisor_desc_bin = binary('1up-hv.bin')
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self.partition_desc_bin = binary('1up-md.bin')
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self.system_port = self.membus.slave
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return self
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def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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dtb_filename=None, bare_metal=False, cmdline=None,
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external_memory=""):
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assert machine_type
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default_dtbs = {
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"RealViewEB": None,
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"RealViewPBX": None,
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"VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus,
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"VExpress_EMM64": "vexpress.aarch64.20140821.dtb",
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}
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default_kernels = {
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"RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8",
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"RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8",
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"VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5",
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"VExpress_EMM64": "vmlinux.aarch64.20140821",
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}
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if bare_metal:
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self = ArmSystem()
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else:
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self = LinuxArmSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = IOXBar()
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self.membus = MemBus()
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self.membus.badaddr_responder.warn_access = "warn"
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self.bridge = Bridge(delay='50ns')
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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self.mem_mode = mem_mode
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platform_class = PlatformConfig.get(machine_type)
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# Resolve the real platform name, the original machine_type
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# variable might have been an alias.
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machine_type = platform_class.__name__
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self.realview = platform_class()
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if not dtb_filename and not bare_metal:
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try:
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dtb_filename = default_dtbs[machine_type]
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except KeyError:
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fatal("No DTB specified and no default DTB known for '%s'" % \
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machine_type)
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if isinstance(self.realview, VExpress_EMM64):
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if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
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print "Selected 64-bit ARM architecture, updating default disk image..."
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mdesc.diskname = 'linaro-minimal-aarch64.img'
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self.cf0 = CowIdeDisk(driveID='master')
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self.cf0.childImage(mdesc.disk())
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# Attach any PCI devices this platform supports
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self.realview.attachPciDevices()
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# default to an IDE controller rather than a CF one
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try:
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self.realview.ide.disks = [self.cf0]
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except:
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self.realview.cf_ctrl.disks = [self.cf0]
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self.mem_ranges = []
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size_remain = long(Addr(mdesc.mem()))
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for region in self.realview._mem_regions:
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if size_remain > long(region[1]):
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self.mem_ranges.append(AddrRange(region[0], size=region[1]))
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size_remain = size_remain - long(region[1])
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else:
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self.mem_ranges.append(AddrRange(region[0], size=size_remain))
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size_remain = 0
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break
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warn("Memory size specified spans more than one region. Creating" \
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" another memory controller for that range.")
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if size_remain > 0:
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fatal("The currently selected ARM platforms doesn't support" \
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" the amount of DRAM you've selected. Please try" \
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" another platform")
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if bare_metal:
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# EOT character on UART will end the simulation
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self.realview.uart.end_on_eot = True
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else:
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if machine_type in default_kernels:
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self.kernel = binary(default_kernels[machine_type])
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if dtb_filename:
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self.dtb_filename = binary(dtb_filename)
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self.machine_type = machine_type if machine_type in ArmMachineType.map \
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else "DTOnly"
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# Ensure that writes to the UART actually go out early in the boot
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if not cmdline:
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cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
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'lpj=19988480 norandmaps rw loglevel=8 ' + \
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'mem=%(mem)s root=%(rootdev)s'
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# When using external memory, gem5 writes the boot loader to nvmem
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# and then SST will read from it, but SST can only get to nvmem from
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# iobus, as gem5's membus is only used for initialization and
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# SST doesn't use it. Attaching nvmem to iobus solves this issue.
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# During initialization, system_port -> membus -> iobus -> nvmem.
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if external_memory:
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self.realview.setupBootLoader(self.iobus, self, binary)
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else:
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self.realview.setupBootLoader(self.membus, self, binary)
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.flags_addr = self.realview.realview_io.pio_addr + 0x30
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# This check is for users who have previously put 'android' in
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# the disk image filename to tell the config scripts to
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# prepare the kernel with android-specific boot options. That
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# behavior has been replaced with a more explicit option per
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# the error message below. The disk can have any name now and
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# doesn't need to include 'android' substring.
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if (os.path.split(mdesc.disk())[-1]).lower().count('android'):
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if 'android' not in mdesc.os_type():
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fatal("It looks like you are trying to boot an Android " \
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"platform. To boot Android, you must specify " \
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"--os-type with an appropriate Android release on " \
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"the command line.")
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# android-specific tweaks
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if 'android' in mdesc.os_type():
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# generic tweaks
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cmdline += " init=/init"
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# release-specific tweaks
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if 'kitkat' in mdesc.os_type():
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cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
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"android.bootanim=0"
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self.boot_osflags = fillInCmdline(mdesc, cmdline)
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if external_memory:
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# I/O traffic enters iobus
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self.external_io = ExternalMaster(port_data="external_io",
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port_type=external_memory)
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self.external_io.port = self.iobus.slave
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# Ensure iocache only receives traffic destined for (actual) memory.
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self.iocache = ExternalSlave(port_data="iocache",
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port_type=external_memory,
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addr_ranges=self.mem_ranges)
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self.iocache.port = self.iobus.master
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# Let system_port get to nvmem and nothing else.
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self.bridge.ranges = [self.realview.nvmem.range]
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self.realview.attachOnChipIO(self.iobus)
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else:
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self.realview.attachOnChipIO(self.membus, self.bridge)
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self.realview.attachIO(self.iobus)
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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self.vncserver = VncServer()
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self.system_port = self.membus.slave
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return self
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def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
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class BaseMalta(Malta):
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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self = LinuxMipsSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = IOXBar()
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self.membus = MemBus()
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self.bridge = Bridge(delay='50ns')
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self.mem_ranges = [AddrRange('1GB')]
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(mdesc.disk())
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.malta = BaseMalta()
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self.malta.attachIO(self.iobus)
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self.malta.ide.pio = self.iobus.master
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self.malta.ide.dma = self.iobus.slave
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self.malta.ethernet.pio = self.iobus.master
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self.malta.ethernet.dma = self.iobus.slave
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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self.intrctrl = IntrControl()
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self.mem_mode = mem_mode
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self.terminal = Terminal()
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self.kernel = binary('mips/vmlinux')
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self.console = binary('mips/console')
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if not cmdline:
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cmdline = 'root=/dev/hda1 console=ttyS0'
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self.boot_osflags = fillInCmdline(mdesc, cmdline)
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self.system_port = self.membus.slave
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return self
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def x86IOAddress(port):
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IO_address_space_base = 0x8000000000000000
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return IO_address_space_base + port
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def connectX86ClassicSystem(x86_sys, numCPUs):
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# Constants similar to x86_traits.hh
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IO_address_space_base = 0x8000000000000000
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pci_config_address_space_base = 0xc000000000000000
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interrupts_address_space_base = 0xa000000000000000
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APIC_range_size = 1 << 12;
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x86_sys.membus = MemBus()
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# North Bridge
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x86_sys.iobus = IOXBar()
|
|
x86_sys.bridge = Bridge(delay='50ns')
|
|
x86_sys.bridge.master = x86_sys.iobus.slave
|
|
x86_sys.bridge.slave = x86_sys.membus.master
|
|
# Allow the bridge to pass through:
|
|
# 1) kernel configured PCI device memory map address: address range
|
|
# [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
|
|
# 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
|
|
# 3) everything in the IO address range up to the local APIC, and
|
|
# 4) then the entire PCI address space and beyond.
|
|
x86_sys.bridge.ranges = \
|
|
[
|
|
AddrRange(0xC0000000, 0xFFFF0000),
|
|
AddrRange(IO_address_space_base,
|
|
interrupts_address_space_base - 1),
|
|
AddrRange(pci_config_address_space_base,
|
|
Addr.max)
|
|
]
|
|
|
|
# Create a bridge from the IO bus to the memory bus to allow access to
|
|
# the local APIC (two pages)
|
|
x86_sys.apicbridge = Bridge(delay='50ns')
|
|
x86_sys.apicbridge.slave = x86_sys.iobus.master
|
|
x86_sys.apicbridge.master = x86_sys.membus.slave
|
|
x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
|
|
interrupts_address_space_base +
|
|
numCPUs * APIC_range_size
|
|
- 1)]
|
|
|
|
# connect the io bus
|
|
x86_sys.pc.attachIO(x86_sys.iobus)
|
|
|
|
x86_sys.system_port = x86_sys.membus.slave
|
|
|
|
def connectX86RubySystem(x86_sys):
|
|
# North Bridge
|
|
x86_sys.iobus = IOXBar()
|
|
|
|
# add the ide to the list of dma devices that later need to attach to
|
|
# dma controllers
|
|
x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
|
|
x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
|
|
|
|
|
|
def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
|
|
if self == None:
|
|
self = X86System()
|
|
|
|
if not mdesc:
|
|
# generic system
|
|
mdesc = SysConfig()
|
|
self.readfile = mdesc.script()
|
|
|
|
self.mem_mode = mem_mode
|
|
|
|
# Physical memory
|
|
# On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
|
|
# for various devices. Hence, if the physical memory size is greater than
|
|
# 3GB, we need to split it into two parts.
|
|
excess_mem_size = \
|
|
convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
|
|
if excess_mem_size <= 0:
|
|
self.mem_ranges = [AddrRange(mdesc.mem())]
|
|
else:
|
|
warn("Physical memory size specified is %s which is greater than " \
|
|
"3GB. Twice the number of memory controllers would be " \
|
|
"created." % (mdesc.mem()))
|
|
|
|
self.mem_ranges = [AddrRange('3GB'),
|
|
AddrRange(Addr('4GB'), size = excess_mem_size)]
|
|
|
|
# Platform
|
|
self.pc = Pc()
|
|
|
|
# Create and connect the busses required by each memory system
|
|
if Ruby:
|
|
connectX86RubySystem(self)
|
|
else:
|
|
connectX86ClassicSystem(self, numCPUs)
|
|
|
|
self.intrctrl = IntrControl()
|
|
|
|
# Disks
|
|
disk0 = CowIdeDisk(driveID='master')
|
|
disk2 = CowIdeDisk(driveID='master')
|
|
disk0.childImage(mdesc.disk())
|
|
disk2.childImage(disk('linux-bigswap2.img'))
|
|
self.pc.south_bridge.ide.disks = [disk0, disk2]
|
|
|
|
# Add in a Bios information structure.
|
|
structures = [X86SMBiosBiosInformation()]
|
|
self.smbios_table.structures = structures
|
|
|
|
# Set up the Intel MP table
|
|
base_entries = []
|
|
ext_entries = []
|
|
for i in xrange(numCPUs):
|
|
bp = X86IntelMPProcessor(
|
|
local_apic_id = i,
|
|
local_apic_version = 0x14,
|
|
enable = True,
|
|
bootstrap = (i == 0))
|
|
base_entries.append(bp)
|
|
io_apic = X86IntelMPIOAPIC(
|
|
id = numCPUs,
|
|
version = 0x11,
|
|
enable = True,
|
|
address = 0xfec00000)
|
|
self.pc.south_bridge.io_apic.apic_id = io_apic.id
|
|
base_entries.append(io_apic)
|
|
# In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
|
|
# but linux kernel cannot config PCI device if it was not connected to PCI bus,
|
|
# so we fix PCI bus id to 0, and ISA bus id to 1.
|
|
pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI')
|
|
base_entries.append(pci_bus)
|
|
isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA')
|
|
base_entries.append(isa_bus)
|
|
connect_busses = X86IntelMPBusHierarchy(bus_id=1,
|
|
subtractive_decode=True, parent_bus=0)
|
|
ext_entries.append(connect_busses)
|
|
pci_dev4_inta = X86IntelMPIOIntAssignment(
|
|
interrupt_type = 'INT',
|
|
polarity = 'ConformPolarity',
|
|
trigger = 'ConformTrigger',
|
|
source_bus_id = 0,
|
|
source_bus_irq = 0 + (4 << 2),
|
|
dest_io_apic_id = io_apic.id,
|
|
dest_io_apic_intin = 16)
|
|
base_entries.append(pci_dev4_inta)
|
|
def assignISAInt(irq, apicPin):
|
|
assign_8259_to_apic = X86IntelMPIOIntAssignment(
|
|
interrupt_type = 'ExtInt',
|
|
polarity = 'ConformPolarity',
|
|
trigger = 'ConformTrigger',
|
|
source_bus_id = 1,
|
|
source_bus_irq = irq,
|
|
dest_io_apic_id = io_apic.id,
|
|
dest_io_apic_intin = 0)
|
|
base_entries.append(assign_8259_to_apic)
|
|
assign_to_apic = X86IntelMPIOIntAssignment(
|
|
interrupt_type = 'INT',
|
|
polarity = 'ConformPolarity',
|
|
trigger = 'ConformTrigger',
|
|
source_bus_id = 1,
|
|
source_bus_irq = irq,
|
|
dest_io_apic_id = io_apic.id,
|
|
dest_io_apic_intin = apicPin)
|
|
base_entries.append(assign_to_apic)
|
|
assignISAInt(0, 2)
|
|
assignISAInt(1, 1)
|
|
for i in range(3, 15):
|
|
assignISAInt(i, i)
|
|
self.intel_mp_table.base_entries = base_entries
|
|
self.intel_mp_table.ext_entries = ext_entries
|
|
|
|
def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
|
|
cmdline=None):
|
|
self = LinuxX86System()
|
|
|
|
# Build up the x86 system and then specialize it for Linux
|
|
makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
|
|
|
|
# We assume below that there's at least 1MB of memory. We'll require 2
|
|
# just to avoid corner cases.
|
|
phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
|
|
assert(phys_mem_size >= 0x200000)
|
|
assert(len(self.mem_ranges) <= 2)
|
|
|
|
entries = \
|
|
[
|
|
# Mark the first megabyte of memory as reserved
|
|
X86E820Entry(addr = 0, size = '639kB', range_type = 1),
|
|
X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
|
|
# Mark the rest of physical memory as available
|
|
X86E820Entry(addr = 0x100000,
|
|
size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
|
|
range_type = 1),
|
|
]
|
|
|
|
# Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
|
|
# IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
|
|
# specific range can pass though bridge to iobus.
|
|
if len(self.mem_ranges) == 1:
|
|
entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
|
|
size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
|
|
range_type=2))
|
|
|
|
# Reserve the last 16kB of the 32-bit address space for the m5op interface
|
|
entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
|
|
|
|
# In case the physical memory is greater than 3GB, we split it into two
|
|
# parts and add a separate e820 entry for the second part. This entry
|
|
# starts at 0x100000000, which is the first address after the space
|
|
# reserved for devices.
|
|
if len(self.mem_ranges) == 2:
|
|
entries.append(X86E820Entry(addr = 0x100000000,
|
|
size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
|
|
|
|
self.e820_table.entries = entries
|
|
|
|
# Command line
|
|
if not cmdline:
|
|
cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
|
|
self.boot_osflags = fillInCmdline(mdesc, cmdline)
|
|
self.kernel = binary('x86_64-vmlinux-2.6.22.9')
|
|
return self
|
|
|
|
|
|
def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
|
|
self = Root(full_system = full_system)
|
|
self.testsys = testSystem
|
|
self.drivesys = driveSystem
|
|
self.etherlink = EtherLink()
|
|
|
|
if hasattr(testSystem, 'realview'):
|
|
self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
|
|
self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
|
|
elif hasattr(testSystem, 'tsunami'):
|
|
self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
|
|
self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
|
|
else:
|
|
fatal("Don't know how to connect these system together")
|
|
|
|
if dumpfile:
|
|
self.etherdump = EtherDump(file=dumpfile)
|
|
self.etherlink.dump = Parent.etherdump
|
|
|
|
return self
|