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gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
Andreas Hansson 25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes 
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.647861 # Number of seconds simulated
sim_ticks 1647861059500 # Number of ticks simulated
final_tick 1647861059500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 708384 # Simulator instruction rate (inst/s)
host_op_rate 1309882 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1411719986 # Simulator tick rate (ticks/s)
host_mem_usage 323600 # Number of bytes of host memory used
host_seconds 1167.27 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 120384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24254848 # Number of bytes read from this memory
system.physmem.bytes_read::total 24375232 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 120384 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 120384 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18763136 # Number of bytes written to this memory
system.physmem.bytes_written::total 18763136 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1881 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 378982 # Number of read requests responded to by this memory
system.physmem.num_reads::total 380863 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293174 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293174 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 73055 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14718989 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14792043 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 73055 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 73055 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11386358 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11386358 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11386358 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 73055 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14718989 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26178401 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3295722119 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877110 # Number of instructions committed
system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
system.cpu.num_int_insts 1526605510 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read
system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written
system.cpu.num_mem_refs 533262343 # number of memory refs
system.cpu.num_load_insts 384102157 # Number of load instructions
system.cpu.num_store_insts 149160186 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 3295722118.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 149758583 # Number of branches fetched
system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction
system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction
system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction
system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction
system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1528988702 # Class of executed instruction
system.cpu.dcache.tags.replacements 2514362 # number of replacements
system.cpu.dcache.tags.tagsinuse 4086.415711 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 8211725500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415711 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits
system.cpu.dcache.overall_hits::total 530743930 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29707934500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 29707934500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18949311500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 18949311500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 48657246000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 48657246000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 48657246000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 48657246000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17197.923891 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17197.923891 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23954.813512 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23954.813512 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19320.253107 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19320.253107 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2323227 # number of writebacks
system.cpu.dcache.writebacks::total 2323227 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27980520500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 27980520500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18158267500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 18158267500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46138788000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 46138788000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46138788000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 46138788000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16197.923891 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16197.923891 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22954.813512 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22954.813512 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1253 # number of replacements
system.cpu.icache.tags.tagsinuse 881.348726 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 881.348726 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.430346 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.430346 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2136696944 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2136696944 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1068344251 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068344251 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068344251 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068344251 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068344251 # number of overall hits
system.cpu.icache.overall_hits::total 1068344251 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
system.cpu.icache.overall_misses::total 2814 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 115655000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 115655000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 115655000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 115655000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 115655000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 115655000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1068347065 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1068347065 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1068347065 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41099.857854 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 41099.857854 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 41099.857854 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 41099.857854 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112841000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 112841000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112841000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 112841000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112841000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 112841000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40099.857854 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40099.857854 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 348182 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29285.938694 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3846845 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 380537 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.108991 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 755943397500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 20928.501607 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.116925 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8218.320163 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.638687 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004246 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.250803 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.893736 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24069 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 41466677 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41466677 # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks 2323227 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2323227 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 584717 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 584717 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 933 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 933 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1554759 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1554759 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 933 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2139476 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2140409 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 933 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2139476 # number of overall hits
system.cpu.l2cache.overall_hits::total 2140409 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 206327 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206327 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1881 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1881 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172655 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 172655 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1881 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 378982 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 380863 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1881 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 378982 # number of overall misses
system.cpu.l2cache.overall_misses::total 380863 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10832173000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 10832173000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 98817000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 98817000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9064428500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 9064428500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 98817000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 19896601500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 19995418500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 98817000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 19896601500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 19995418500 # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks 2323227 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2323227 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1727414 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1727414 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260829 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.260829 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.668443 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.668443 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099950 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099950 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.668443 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150482 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.151060 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.668443 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150482 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.151060 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.026657 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.026657 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52534.290271 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52534.290271 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.237468 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.237468 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52534.290271 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.122697 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52500.291443 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52534.290271 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.122697 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52500.291443 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 293174 # number of writebacks
system.cpu.l2cache.writebacks::total 293174 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 275 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 275 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206327 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206327 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1881 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1881 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172655 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172655 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1881 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 378982 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 380863 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1881 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 378982 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 380863 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8768903000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8768903000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 80007000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 80007000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7337878500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7337878500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 80007000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16106781500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16186788500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 80007000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16106781500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16186788500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260829 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260829 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.668443 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099950 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099950 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151060 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151060 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.026657 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.026657 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42534.290271 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42534.290271 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.237468 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.237468 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2616401 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 247396 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1727414 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7551278 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7558159 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309867840 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 310047936 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 348182 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 5385069 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.064657 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.245920 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 5036887 93.53% 93.53% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 348182 6.47% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 5385069 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4841670500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 174536 # Transaction distribution
system.membus.trans_dist::Writeback 293174 # Transaction distribution
system.membus.trans_dist::CleanEvict 53553 # Transaction distribution
system.membus.trans_dist::ReadExReq 206327 # Transaction distribution
system.membus.trans_dist::ReadExResp 206327 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 174536 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108453 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108453 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1108453 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43138368 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43138368 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43138368 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 727623 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 727623 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 727623 # Request fanout histogram
system.membus.reqLayer0.occupancy 1900350576 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 1904342076 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
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