844 lines
25 KiB
C++
844 lines
25 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#ifndef __CPU_INORDER_CPU_HH__
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#define __CPU_INORDER_CPU_HH__
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#include <iostream>
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#include <list>
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#include <queue>
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#include <set>
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#include <vector>
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#include "arch/isa_traits.hh"
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#include "arch/types.hh"
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#include "arch/registers.hh"
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#include "base/statistics.hh"
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#include "cpu/timebuf.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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#include "config/the_isa.hh"
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#include "cpu/activity.hh"
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#include "cpu/base.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/pipeline_stage.hh"
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#include "cpu/inorder/thread_state.hh"
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#include "cpu/inorder/reg_dep_map.hh"
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#include "cpu/o3/dep_graph.hh"
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#include "cpu/o3/rename_map.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "mem/request.hh"
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#include "sim/eventq.hh"
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#include "sim/process.hh"
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class ThreadContext;
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class MemInterface;
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class MemObject;
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class Process;
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class ResourcePool;
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class InOrderCPU : public BaseCPU
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{
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protected:
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typedef ThePipeline::Params Params;
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typedef InOrderThreadState Thread;
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//ISA TypeDefs
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::MiscReg MiscReg;
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//DynInstPtr TypeDefs
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typedef ThePipeline::DynInstPtr DynInstPtr;
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typedef std::list<DynInstPtr>::iterator ListIt;
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//TimeBuffer TypeDefs
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typedef TimeBuffer<InterStageStruct> StageQueue;
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friend class Resource;
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public:
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/** Constructs a CPU with the given parameters. */
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InOrderCPU(Params *params);
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/* Destructor */
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~InOrderCPU();
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/** CPU ID */
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int cpu_id;
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// SE Mode ASIDs
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ThreadID asid[ThePipeline::MaxThreads];
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/** Type of core that this is */
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std::string coreType;
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// Only need for SE MODE
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enum ThreadModel {
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Single,
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SMT,
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SwitchOnCacheMiss
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};
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ThreadModel threadModel;
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int readCpuId() { return cpu_id; }
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void setCpuId(int val) { cpu_id = val; }
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Params *cpu_params;
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public:
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enum Status {
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Running,
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Idle,
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Halted,
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Blocked,
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SwitchedOut
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};
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/** Overall CPU status. */
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Status _status;
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private:
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/** Define TickEvent for the CPU */
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class TickEvent : public Event
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{
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private:
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/** Pointer to the CPU. */
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InOrderCPU *cpu;
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public:
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/** Constructs a tick event. */
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TickEvent(InOrderCPU *c);
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/** Processes a tick event, calling tick() on the CPU. */
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void process();
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/** Returns the description of the tick event. */
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const char *description();
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};
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/** The tick event used for scheduling CPU ticks. */
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TickEvent tickEvent;
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/** Schedule tick event, regardless of its current state. */
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void scheduleTickEvent(int delay)
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{
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assert(!tickEvent.scheduled() || tickEvent.squashed());
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reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
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}
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/** Unschedule tick event, regardless of its current state. */
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void unscheduleTickEvent()
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{
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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public:
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// List of Events That can be scheduled from
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// within the CPU.
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// NOTE(1): The Resource Pool also uses this event list
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// to schedule events broadcast to all resources interfaces
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// NOTE(2): CPU Events usually need to schedule a corresponding resource
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// pool event.
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enum CPUEventType {
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ActivateThread,
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ActivateNextReadyThread,
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DeactivateThread,
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HaltThread,
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SuspendThread,
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Trap,
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InstGraduated,
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SquashFromMemStall,
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UpdatePCs,
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NumCPUEvents
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};
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static std::string eventNames[NumCPUEvents];
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/** Define CPU Event */
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class CPUEvent : public Event
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{
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protected:
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InOrderCPU *cpu;
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public:
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CPUEventType cpuEventType;
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ThreadID tid;
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DynInstPtr inst;
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Fault fault;
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unsigned vpe;
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public:
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/** Constructs a CPU event. */
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CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
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ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
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/** Set Type of Event To Be Scheduled */
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void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
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DynInstPtr _inst)
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{
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fault = _fault;
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cpuEventType = e_type;
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tid = _tid;
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inst = _inst;
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vpe = 0;
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}
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/** Processes a CPU event. */
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void process();
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/** Returns the description of the CPU event. */
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const char *description();
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/** Schedule Event */
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void scheduleEvent(int delay);
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/** Unschedule This Event */
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void unscheduleEvent();
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};
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/** Schedule a CPU Event */
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void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
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DynInstPtr inst, unsigned delay = 0,
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unsigned event_pri_offset = 0);
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public:
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/** Interface between the CPU and CPU resources. */
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ResourcePool *resPool;
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/** Instruction used to signify that there is no *real* instruction in
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buffer slot */
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DynInstPtr dummyInst[ThePipeline::MaxThreads];
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DynInstPtr dummyBufferInst;
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DynInstPtr dummyReqInst;
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/** Used by resources to signify a denied access to a resource. */
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ResourceRequest *dummyReq[ThePipeline::MaxThreads];
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/** Identifies the resource id that identifies a fetch
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* access unit.
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*/
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unsigned fetchPortIdx;
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/** Identifies the resource id that identifies a ITB */
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unsigned itbIdx;
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/** Identifies the resource id that identifies a data
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* access unit.
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*/
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unsigned dataPortIdx;
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/** Identifies the resource id that identifies a DTB */
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unsigned dtbIdx;
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/** The Pipeline Stages for the CPU */
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PipelineStage *pipelineStage[ThePipeline::NumStages];
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/** Width (processing bandwidth) of each stage */
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int stageWidth;
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/** Program Counters */
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TheISA::PCState pc[ThePipeline::MaxThreads];
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/** The Register File for the CPU */
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union {
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FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
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FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
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} floatRegs;
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TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
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/** ISA state */
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TheISA::ISA isa[ThePipeline::MaxThreads];
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/** Dependency Tracker for Integer & Floating Point Regs */
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RegDepMap archRegDepMap[ThePipeline::MaxThreads];
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/** Global communication structure */
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TimeBuffer<TimeStruct> timeBuffer;
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/** Communication structure that sits in between pipeline stages */
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StageQueue *stageQueue[ThePipeline::NumStages-1];
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TheISA::TLB *getITBPtr();
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TheISA::TLB *getDTBPtr();
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/** Accessor Type for the SkedCache */
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typedef uint32_t SkedID;
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/** Cache of Instruction Schedule using the instruction's name as a key */
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static std::map<SkedID, ThePipeline::RSkedPtr> skedCache;
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typedef std::map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
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/** Initialized to last iterator in map, signifying a invalid entry
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on map searches
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*/
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SkedCacheIt endOfSkedIt;
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ThePipeline::RSkedPtr frontEndSked;
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/** Add a new instruction schedule to the schedule cache */
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void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
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{
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SkedID sked_id = genSkedID(inst);
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assert(skedCache.find(sked_id) == skedCache.end());
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skedCache[sked_id] = inst_sked;
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}
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/** Find a instruction schedule */
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ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
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{
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SkedID sked_id = genSkedID(inst);
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SkedCacheIt lookup_it = skedCache.find(sked_id);
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if (lookup_it != endOfSkedIt) {
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return (*lookup_it).second;
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} else {
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return NULL;
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}
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}
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static const uint8_t INST_OPCLASS = 26;
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static const uint8_t INST_LOAD = 25;
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static const uint8_t INST_STORE = 24;
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static const uint8_t INST_CONTROL = 23;
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static const uint8_t INST_NONSPEC = 22;
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static const uint8_t INST_DEST_REGS = 18;
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static const uint8_t INST_SRC_REGS = 14;
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inline SkedID genSkedID(DynInstPtr inst)
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{
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SkedID id = 0;
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id = (inst->opClass() << INST_OPCLASS) |
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(inst->isLoad() << INST_LOAD) |
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(inst->isStore() << INST_STORE) |
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(inst->isControl() << INST_CONTROL) |
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(inst->isNonSpeculative() << INST_NONSPEC) |
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(inst->numDestRegs() << INST_DEST_REGS) |
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(inst->numSrcRegs() << INST_SRC_REGS);
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return id;
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}
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ThePipeline::RSkedPtr createFrontEndSked();
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ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
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class StageScheduler {
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private:
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ThePipeline::RSkedPtr rsked;
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int stageNum;
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int nextTaskPriority;
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public:
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StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
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: rsked(_rsked), stageNum(stage_num),
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nextTaskPriority(0)
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{ }
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void needs(int unit, int request) {
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rsked->push(new ScheduleEntry(
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stageNum, nextTaskPriority++, unit, request
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));
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}
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void needs(int unit, int request, int param) {
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rsked->push(new ScheduleEntry(
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stageNum, nextTaskPriority++, unit, request, param
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));
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}
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};
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public:
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/** Registers statistics. */
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void regStats();
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/** Ticks CPU, calling tick() on each stage, and checking the overall
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* activity to see if the CPU should deschedule itself.
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*/
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void tick();
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/** Initialize the CPU */
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void init();
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/** Reset State in the CPU */
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void reset();
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/** Get a Memory Port */
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Port* getPort(const std::string &if_name, int idx = 0);
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#if FULL_SYSTEM
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/** HW return from error interrupt. */
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Fault hwrei(ThreadID tid);
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bool simPalCheck(int palFunc, ThreadID tid);
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/** Returns the Fault for any valid interrupt. */
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Fault getInterrupts();
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/** Processes any an interrupt fault. */
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void processInterrupts(Fault interrupt);
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/** Halts the CPU. */
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void halt() { panic("Halt not implemented!\n"); }
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/** Update the Virt and Phys ports of all ThreadContexts to
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* reflect change in memory connections. */
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void updateMemPorts();
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/** Check if this address is a valid instruction address. */
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bool validInstAddr(Addr addr) { return true; }
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/** Check if this address is a valid data address. */
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bool validDataAddr(Addr addr) { return true; }
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#endif
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/** trap() - sets up a trap event on the cpuTraps to handle given fault.
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* trapCPU() - Traps to handle given fault
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*/
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void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
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void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
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/** Add Thread to Active Threads List. */
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void activateContext(ThreadID tid, int delay = 0);
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void activateThread(ThreadID tid);
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void activateThreadInPipeline(ThreadID tid);
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/** Add Thread to Active Threads List. */
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void activateNextReadyContext(int delay = 0);
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void activateNextReadyThread();
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/** Remove from Active Thread List */
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void deactivateContext(ThreadID tid, int delay = 0);
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void deactivateThread(ThreadID tid);
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/** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
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void suspendContext(ThreadID tid, int delay = 0);
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void suspendThread(ThreadID tid);
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/** Halt Thread, Remove from Active Thread List, Place Thread on Halted
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* Threads List
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*/
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void haltContext(ThreadID tid, int delay = 0);
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void haltThread(ThreadID tid);
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/** squashFromMemStall() - sets up a squash event
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* squashDueToMemStall() - squashes pipeline
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* @note: maybe squashContext/squashThread would be better?
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*/
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void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
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void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
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void removePipelineStalls(ThreadID tid);
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void squashThreadInPipeline(ThreadID tid);
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void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
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PipelineStage* getPipeStage(int stage_num);
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int
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contextId()
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{
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hack_once("return a bogus context id");
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return 0;
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}
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/** Update The Order In Which We Process Threads. */
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void updateThreadPriority();
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/** Switches a Pipeline Stage to Active. (Unused currently) */
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void switchToActive(int stage_idx)
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{ /*pipelineStage[stage_idx]->switchToActive();*/ }
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/** Get the current instruction sequence number, and increment it. */
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InstSeqNum getAndIncrementInstSeq(ThreadID tid)
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{ return globalSeqNum[tid]++; }
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/** Get the current instruction sequence number, and increment it. */
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InstSeqNum nextInstSeqNum(ThreadID tid)
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{ return globalSeqNum[tid]; }
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/** Increment Instruction Sequence Number */
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void incrInstSeqNum(ThreadID tid)
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{ globalSeqNum[tid]++; }
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/** Set Instruction Sequence Number */
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void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
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{
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globalSeqNum[tid] = seq_num;
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}
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/** Get & Update Next Event Number */
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InstSeqNum getNextEventNum()
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{
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#ifdef DEBUG
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return cpuEventNum++;
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#else
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return 0;
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#endif
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}
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/** Register file accessors */
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uint64_t readIntReg(int reg_idx, ThreadID tid);
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FloatReg readFloatReg(int reg_idx, ThreadID tid);
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FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
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void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
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void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
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void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid);
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/** Reads a miscellaneous register. */
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MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
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/** Reads a misc. register, including any side effects the read
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* might have as defined by the architecture.
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*/
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MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
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/** Sets a miscellaneous register. */
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
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ThreadID tid = 0);
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/** Sets a misc. register, including any side effects the write
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* might have as defined by the architecture.
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*/
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void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
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/** Reads a int/fp/misc reg. from another thread depending on ISA-defined
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* target thread
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*/
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uint64_t readRegOtherThread(unsigned misc_reg,
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ThreadID tid = InvalidThreadID);
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|
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/** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
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* target thread
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*/
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void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
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ThreadID tid);
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|
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/** Reads the commit PC of a specific thread. */
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|
TheISA::PCState
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pcState(ThreadID tid)
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{
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return pc[tid];
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}
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|
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/** Sets the commit PC of a specific thread. */
|
|
void
|
|
pcState(const TheISA::PCState &newPC, ThreadID tid)
|
|
{
|
|
pc[tid] = newPC;
|
|
}
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|
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Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
|
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Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
|
|
MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
|
|
|
|
/** Function to add instruction onto the head of the list of the
|
|
* instructions. Used when new instructions are fetched.
|
|
*/
|
|
ListIt addInst(DynInstPtr &inst);
|
|
|
|
/** Function to tell the CPU that an instruction has completed. */
|
|
void instDone(DynInstPtr inst, ThreadID tid);
|
|
|
|
/** Add Instructions to the CPU Remove List*/
|
|
void addToRemoveList(DynInstPtr &inst);
|
|
|
|
/** Remove an instruction from CPU */
|
|
void removeInst(DynInstPtr &inst);
|
|
|
|
/** Remove all instructions younger than the given sequence number. */
|
|
void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
|
|
|
|
/** Removes the instruction pointed to by the iterator. */
|
|
inline void squashInstIt(const ListIt &instIt, ThreadID tid);
|
|
|
|
/** Cleans up all instructions on the instruction remove list. */
|
|
void cleanUpRemovedInsts();
|
|
|
|
/** Cleans up all events on the CPU event remove list. */
|
|
void cleanUpRemovedEvents();
|
|
|
|
/** Debug function to print all instructions on the list. */
|
|
void dumpInsts();
|
|
|
|
/** Forwards an instruction read to the appropriate data
|
|
* resource (indexes into Resource Pool thru "dataPortIdx")
|
|
*/
|
|
Fault read(DynInstPtr inst, Addr addr,
|
|
uint8_t *data, unsigned size, unsigned flags);
|
|
|
|
/** Forwards an instruction write. to the appropriate data
|
|
* resource (indexes into Resource Pool thru "dataPortIdx")
|
|
*/
|
|
Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
|
|
Addr addr, unsigned flags, uint64_t *write_res = NULL);
|
|
|
|
/** Executes a syscall.*/
|
|
void syscall(int64_t callnum, ThreadID tid);
|
|
|
|
public:
|
|
/** Per-Thread List of all the instructions in flight. */
|
|
std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
|
|
|
|
/** List of all the instructions that will be removed at the end of this
|
|
* cycle.
|
|
*/
|
|
std::queue<ListIt> removeList;
|
|
|
|
/** List of all the cpu event requests that will be removed at the end of
|
|
* the current cycle.
|
|
*/
|
|
std::queue<Event*> cpuEventRemoveList;
|
|
|
|
/** Records if instructions need to be removed this cycle due to
|
|
* being retired or squashed.
|
|
*/
|
|
bool removeInstsThisCycle;
|
|
|
|
/** True if there is non-speculative Inst Active In Pipeline. Lets any
|
|
* execution unit know, NOT to execute while the instruction is active.
|
|
*/
|
|
bool nonSpecInstActive[ThePipeline::MaxThreads];
|
|
|
|
/** Instruction Seq. Num of current non-speculative instruction. */
|
|
InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
|
|
|
|
/** Instruction Seq. Num of last instruction squashed in pipeline */
|
|
InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
|
|
|
|
/** Last Cycle that the CPU squashed instruction end. */
|
|
Tick lastSquashCycle[ThePipeline::MaxThreads];
|
|
|
|
std::list<ThreadID> fetchPriorityList;
|
|
|
|
protected:
|
|
/** Active Threads List */
|
|
std::list<ThreadID> activeThreads;
|
|
|
|
/** Ready Threads List */
|
|
std::list<ThreadID> readyThreads;
|
|
|
|
/** Suspended Threads List */
|
|
std::list<ThreadID> suspendedThreads;
|
|
|
|
/** Halted Threads List */
|
|
std::list<ThreadID> haltedThreads;
|
|
|
|
/** Thread Status Functions */
|
|
bool isThreadActive(ThreadID tid);
|
|
bool isThreadReady(ThreadID tid);
|
|
bool isThreadSuspended(ThreadID tid);
|
|
|
|
private:
|
|
/** The activity recorder; used to tell if the CPU has any
|
|
* activity remaining or if it can go to idle and deschedule
|
|
* itself.
|
|
*/
|
|
ActivityRecorder activityRec;
|
|
|
|
public:
|
|
/** Number of Active Threads in the CPU */
|
|
ThreadID numActiveThreads() { return activeThreads.size(); }
|
|
|
|
/** Thread id of active thread
|
|
* Only used for SwitchOnCacheMiss model.
|
|
* Assumes only 1 thread active
|
|
*/
|
|
ThreadID activeThreadId()
|
|
{
|
|
if (numActiveThreads() > 0)
|
|
return activeThreads.front();
|
|
else
|
|
return InvalidThreadID;
|
|
}
|
|
|
|
|
|
/** Records that there was time buffer activity this cycle. */
|
|
void activityThisCycle() { activityRec.activity(); }
|
|
|
|
/** Changes a stage's status to active within the activity recorder. */
|
|
void activateStage(const int idx)
|
|
{ activityRec.activateStage(idx); }
|
|
|
|
/** Changes a stage's status to inactive within the activity recorder. */
|
|
void deactivateStage(const int idx)
|
|
{ activityRec.deactivateStage(idx); }
|
|
|
|
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
|
|
void wakeCPU();
|
|
|
|
#if FULL_SYSTEM
|
|
virtual void wakeup();
|
|
#endif
|
|
|
|
// LL/SC debug functionality
|
|
unsigned stCondFails;
|
|
|
|
unsigned readStCondFailures()
|
|
{ return stCondFails; }
|
|
|
|
unsigned setStCondFailures(unsigned st_fails)
|
|
{ return stCondFails = st_fails; }
|
|
|
|
/** Returns a pointer to a thread context. */
|
|
ThreadContext *tcBase(ThreadID tid = 0)
|
|
{
|
|
return thread[tid]->getTC();
|
|
}
|
|
|
|
/** Count the Total Instructions Committed in the CPU. */
|
|
virtual Counter totalInstructions() const
|
|
{
|
|
Counter total(0);
|
|
|
|
for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
|
|
total += thread[tid]->numInst;
|
|
|
|
return total;
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
/** Pointer to the system. */
|
|
System *system;
|
|
|
|
/** Pointer to physical memory. */
|
|
PhysicalMemory *physmem;
|
|
#endif
|
|
|
|
/** The global sequence number counter. */
|
|
InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
|
|
|
|
#ifdef DEBUG
|
|
/** The global event number counter. */
|
|
InstSeqNum cpuEventNum;
|
|
|
|
/** Number of resource requests active in CPU **/
|
|
unsigned resReqCount;
|
|
#endif
|
|
|
|
/** Counter of how many stages have completed switching out. */
|
|
int switchCount;
|
|
|
|
/** Pointers to all of the threads in the CPU. */
|
|
std::vector<Thread *> thread;
|
|
|
|
/** Pointer to the icache interface. */
|
|
MemInterface *icacheInterface;
|
|
|
|
/** Pointer to the dcache interface. */
|
|
MemInterface *dcacheInterface;
|
|
|
|
/** Whether or not the CPU should defer its registration. */
|
|
bool deferRegistration;
|
|
|
|
/** Per-Stage Instruction Tracing */
|
|
bool stageTracing;
|
|
|
|
/** The cycle that the CPU was last running, used for statistics. */
|
|
Tick lastRunningCycle;
|
|
|
|
void updateContextSwitchStats();
|
|
unsigned instsPerSwitch;
|
|
Stats::Average instsPerCtxtSwitch;
|
|
Stats::Scalar numCtxtSwitches;
|
|
|
|
/** Update Thread , used for statistic purposes*/
|
|
inline void tickThreadStats();
|
|
|
|
/** Per-Thread Tick */
|
|
Stats::Vector threadCycles;
|
|
|
|
/** Tick for SMT */
|
|
Stats::Scalar smtCycles;
|
|
|
|
/** Stat for total number of times the CPU is descheduled. */
|
|
Stats::Scalar timesIdled;
|
|
|
|
/** Stat for total number of cycles the CPU spends descheduled or no
|
|
* stages active.
|
|
*/
|
|
Stats::Scalar idleCycles;
|
|
|
|
/** Stat for total number of cycles the CPU is active. */
|
|
Stats::Scalar runCycles;
|
|
|
|
/** Percentage of cycles a stage was active */
|
|
Stats::Formula activity;
|
|
|
|
/** Instruction Mix Stats */
|
|
Stats::Scalar comLoads;
|
|
Stats::Scalar comStores;
|
|
Stats::Scalar comBranches;
|
|
Stats::Scalar comNops;
|
|
Stats::Scalar comNonSpec;
|
|
Stats::Scalar comInts;
|
|
Stats::Scalar comFloats;
|
|
|
|
/** Stat for the number of committed instructions per thread. */
|
|
Stats::Vector committedInsts;
|
|
|
|
/** Stat for the number of committed instructions per thread. */
|
|
Stats::Vector smtCommittedInsts;
|
|
|
|
/** Stat for the total number of committed instructions. */
|
|
Stats::Scalar totalCommittedInsts;
|
|
|
|
/** Stat for the CPI per thread. */
|
|
Stats::Formula cpi;
|
|
|
|
/** Stat for the SMT-CPI per thread. */
|
|
Stats::Formula smtCpi;
|
|
|
|
/** Stat for the total CPI. */
|
|
Stats::Formula totalCpi;
|
|
|
|
/** Stat for the IPC per thread. */
|
|
Stats::Formula ipc;
|
|
|
|
/** Stat for the total IPC. */
|
|
Stats::Formula smtIpc;
|
|
|
|
/** Stat for the total IPC. */
|
|
Stats::Formula totalIpc;
|
|
};
|
|
|
|
#endif // __CPU_O3_CPU_HH__
|