d4273cc9a6
This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly.
424 lines
13 KiB
C++
424 lines
13 KiB
C++
/*
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* Copyright (c) 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Thomas Grass
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* Andreas Hansson
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*/
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#ifndef __MEM_COMM_MONITOR_HH__
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#define __MEM_COMM_MONITOR_HH__
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#include "base/statistics.hh"
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#include "base/time.hh"
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#include "mem/mem_object.hh"
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#include "params/CommMonitor.hh"
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#include "proto/protoio.hh"
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/**
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* The communication monitor is a MemObject which can monitor statistics of
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* the communication happening between two ports in the memory system.
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*
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* Currently the following stats are implemented: Histograms of read/write
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* transactions, read/write burst lengths, read/write bandwidth,
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* outstanding read/write requests, read latency and inter transaction time
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* (read-read, write-write, read/write-read/write). Furthermore it allows
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* to capture the number of accesses to an address over time ("heat map").
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* All stats can be disabled from Python.
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*/
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class CommMonitor : public MemObject
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{
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public:
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/** Parameters of communication monitor */
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typedef CommMonitorParams Params;
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const Params* params() const
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{ return reinterpret_cast<const Params*>(_params); }
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/**
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* Constructor based on the Python params
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*
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* @param params Python parameters
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*/
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CommMonitor(Params* params);
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/** Destructor */
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~CommMonitor() {}
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/**
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* Callback to flush and close all open output streams on exit. If
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* we were calling the destructor it could be done there.
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*/
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void closeStreams();
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virtual BaseMasterPort& getMasterPort(const std::string& if_name,
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PortID idx = InvalidPortID);
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virtual BaseSlavePort& getSlavePort(const std::string& if_name,
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PortID idx = InvalidPortID);
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virtual void init();
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/** Register statistics */
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void regStats();
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private:
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/**
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* Sender state class for the monitor so that we can annotate
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* packets with a transmit time and receive time.
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*/
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class CommMonitorSenderState : public Packet::SenderState
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{
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public:
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/**
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* Construct a new sender state and store the time so we can
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* calculate round-trip latency.
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*
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* @param _transmitTime Time of packet transmission
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*/
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CommMonitorSenderState(Tick _transmitTime)
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: transmitTime(_transmitTime)
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{ }
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/** Destructor */
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~CommMonitorSenderState() { }
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/** Tick when request is transmitted */
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Tick transmitTime;
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};
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/**
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* This is the master port of the communication monitor. All recv
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* functions call a function in CommMonitor, where the
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* send function of the slave port is called. Besides this, these
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* functions can also perform actions for capturing statistics.
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*/
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class MonitorMasterPort : public MasterPort
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{
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public:
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MonitorMasterPort(const std::string& _name, CommMonitor& _mon)
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: MasterPort(_name, &_mon), mon(_mon)
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{ }
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protected:
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void recvFunctionalSnoop(PacketPtr pkt)
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{
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mon.recvFunctionalSnoop(pkt);
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}
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Tick recvAtomicSnoop(PacketPtr pkt)
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{
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return mon.recvAtomicSnoop(pkt);
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}
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bool recvTimingResp(PacketPtr pkt)
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{
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return mon.recvTimingResp(pkt);
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}
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void recvTimingSnoopReq(PacketPtr pkt)
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{
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mon.recvTimingSnoopReq(pkt);
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}
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void recvRangeChange()
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{
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mon.recvRangeChange();
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}
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bool isSnooping() const
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{
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return mon.isSnooping();
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}
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void recvRetry()
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{
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mon.recvRetryMaster();
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}
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private:
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CommMonitor& mon;
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};
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/** Instance of master port, facing the memory side */
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MonitorMasterPort masterPort;
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/**
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* This is the slave port of the communication monitor. All recv
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* functions call a function in CommMonitor, where the
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* send function of the master port is called. Besides this, these
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* functions can also perform actions for capturing statistics.
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*/
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class MonitorSlavePort : public SlavePort
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{
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public:
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MonitorSlavePort(const std::string& _name, CommMonitor& _mon)
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: SlavePort(_name, &_mon), mon(_mon)
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{ }
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protected:
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void recvFunctional(PacketPtr pkt)
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{
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mon.recvFunctional(pkt);
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}
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Tick recvAtomic(PacketPtr pkt)
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{
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return mon.recvAtomic(pkt);
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}
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bool recvTimingReq(PacketPtr pkt)
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{
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return mon.recvTimingReq(pkt);
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}
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bool recvTimingSnoopResp(PacketPtr pkt)
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{
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return mon.recvTimingSnoopResp(pkt);
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}
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AddrRangeList getAddrRanges() const
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{
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return mon.getAddrRanges();
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}
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void recvRetry()
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{
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mon.recvRetrySlave();
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}
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private:
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CommMonitor& mon;
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};
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/** Instance of slave port, i.e. on the CPU side */
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MonitorSlavePort slavePort;
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void recvFunctional(PacketPtr pkt);
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void recvFunctionalSnoop(PacketPtr pkt);
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Tick recvAtomic(PacketPtr pkt);
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Tick recvAtomicSnoop(PacketPtr pkt);
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bool recvTimingReq(PacketPtr pkt);
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bool recvTimingResp(PacketPtr pkt);
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void recvTimingSnoopReq(PacketPtr pkt);
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bool recvTimingSnoopResp(PacketPtr pkt);
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AddrRangeList getAddrRanges() const;
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bool isSnooping() const;
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void recvRetryMaster();
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void recvRetrySlave();
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void recvRangeChange();
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void periodicTraceDump();
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/** Stats declarations, all in a struct for convenience. */
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struct MonitorStats
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{
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/** Disable flag for burst length historgrams **/
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bool disableBurstLengthHists;
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/** Histogram of read burst lengths */
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Stats::Histogram readBurstLengthHist;
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/** Histogram of write burst lengths */
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Stats::Histogram writeBurstLengthHist;
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/** Disable flag for the bandwidth histograms */
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bool disableBandwidthHists;
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/**
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* Histogram for read bandwidth per sample window. The
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* internal counter is an unsigned int rather than a stat.
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*/
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unsigned int readBytes;
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Stats::Histogram readBandwidthHist;
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Stats::Formula averageReadBW;
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Stats::Scalar totalReadBytes;
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/**
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* Histogram for write bandwidth per sample window. The
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* internal counter is an unsigned int rather than a stat.
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*/
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unsigned int writtenBytes;
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Stats::Histogram writeBandwidthHist;
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Stats::Formula averageWriteBW;
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Stats::Scalar totalWrittenBytes;
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/** Disable flag for latency histograms. */
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bool disableLatencyHists;
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/** Histogram of read request-to-response latencies */
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Stats::Histogram readLatencyHist;
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/** Histogram of write request-to-response latencies */
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Stats::Histogram writeLatencyHist;
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/** Disable flag for ITT distributions. */
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bool disableITTDists;
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/**
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* Inter transaction time (ITT) distributions. There are
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* histograms of the time between two read, write or arbitrary
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* accesses. The time of a request is the tick at which the
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* request is forwarded by the monitor.
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*/
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Stats::Distribution ittReadRead;
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Stats::Distribution ittWriteWrite;
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Stats::Distribution ittReqReq;
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Tick timeOfLastRead;
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Tick timeOfLastWrite;
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Tick timeOfLastReq;
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/** Disable flag for outstanding histograms. */
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bool disableOutstandingHists;
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/**
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* Histogram of outstanding read requests. Counter for
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* outstanding read requests is an unsigned integer because
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* it should not be reset when stats are reset.
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*/
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Stats::Histogram outstandingReadsHist;
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unsigned int outstandingReadReqs;
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/**
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* Histogram of outstanding write requests. Counter for
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* outstanding write requests is an unsigned integer because
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* it should not be reset when stats are reset.
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*/
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Stats::Histogram outstandingWritesHist;
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unsigned int outstandingWriteReqs;
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/** Disable flag for transaction histograms. */
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bool disableTransactionHists;
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/** Histogram of number of read transactions per time bin */
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Stats::Histogram readTransHist;
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unsigned int readTrans;
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/** Histogram of number of timing write transactions per time bin */
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Stats::Histogram writeTransHist;
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unsigned int writeTrans;
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/** Disable flag for address distributions. */
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bool disableAddrDists;
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/**
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* Histogram of number of read accesses to addresses over
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* time.
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*/
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Stats::SparseHistogram readAddrDist;
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/**
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* Histogram of number of write accesses to addresses over
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* time.
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*/
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Stats::SparseHistogram writeAddrDist;
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/**
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* Create the monitor stats and initialise all the members
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* that are not statistics themselves, but used to control the
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* stats or track values during a sample period.
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*/
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MonitorStats(const CommMonitorParams* params) :
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disableBurstLengthHists(params->disable_burst_length_hists),
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disableBandwidthHists(params->disable_bandwidth_hists),
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readBytes(0), writtenBytes(0),
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disableLatencyHists(params->disable_latency_hists),
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disableITTDists(params->disable_itt_dists),
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timeOfLastRead(0), timeOfLastWrite(0), timeOfLastReq(0),
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disableOutstandingHists(params->disable_outstanding_hists),
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outstandingReadReqs(0), outstandingWriteReqs(0),
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disableTransactionHists(params->disable_transaction_hists),
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readTrans(0), writeTrans(0),
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disableAddrDists(params->disable_addr_dists)
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{ }
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};
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/** This function is called periodically at the end of each time bin */
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void samplePeriodic();
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/** Schedule the first periodic event */
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void startup();
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/** Periodic event called at the end of each simulation time bin */
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EventWrapper<CommMonitor, &CommMonitor::samplePeriodic> samplePeriodicEvent;
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/** Length of simulation time bin*/
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Tick samplePeriodTicks;
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Time samplePeriod;
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/** Address mask for sources of read accesses to be captured */
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Addr readAddrMask;
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/** Address mask for sources of write accesses to be captured */
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Addr writeAddrMask;
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/** Instantiate stats */
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MonitorStats stats;
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/** Output stream for a potential trace. */
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ProtoOutputStream* traceStream;
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};
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#endif //__MEM_COMM_MONITOR_HH__
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