3724fb15fa
Eliminate the VSZ constant that defined the Wavefront size (in numbers of work items); replaced it with a parameter in the GPU.py configuration script. Changed all data structures dependent on the Wavefront size to be dynamically sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at initialization time.
369 lines
12 KiB
C++
369 lines
12 KiB
C++
/*
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* Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lisa Hsu
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*/
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#ifndef __WAVEFRONT_HH__
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#define __WAVEFRONT_HH__
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#include <cassert>
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#include <deque>
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#include <memory>
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#include <stack>
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#include <vector>
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#include "base/misc.hh"
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#include "base/types.hh"
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#include "gpu-compute/condition_register_state.hh"
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#include "gpu-compute/lds_state.hh"
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#include "gpu-compute/misc.hh"
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#include "params/Wavefront.hh"
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#include "sim/sim_object.hh"
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static const int MAX_NUM_INSTS_PER_WF = 12;
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/*
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* Arguments for the hsail opcode call, are user defined and variable length.
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* The hardware/finalizer can support arguments in hardware or use memory to
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* pass arguments. For now, let's assume that an unlimited number of arguments
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* are supported in hardware (the compiler inlines functions whenver it can
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* anyways, so unless someone is interested in the implications of linking/
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* library functions, I think this is a reasonable assumption given the typical
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* size of an OpenCL kernel).
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*
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* Note that call args are different than kernel arguments:
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* * All work-items in a kernel refer the same set of kernel arguments
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* * Each work-item has it's on set of call args. So a call argument at
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* address 0x4 is different for work-item 0 and work-item 1.
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*
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* Ok, the table below shows an example of how we organize the call arguments in
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* the CallArgMem class.
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*
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* int foo(int arg1, double arg2)
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* ___________________________________________________
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* | 0: return.0 | 4: return.1 | ... | 252: return.63 |
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* |---------------------------------------------------|
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* | 256: arg1.0 | 260: arg1.1 | ... | 508: arg1.63 |
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* |---------------------------------------------------|
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* | 512: arg2.0 | 520: arg2.1 | ... | 1016: arg2.63 |
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* ___________________________________________________
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*/
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class CallArgMem
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{
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public:
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// pointer to buffer for storing function arguments
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uint8_t *mem;
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int wfSize;
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// size of function args
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int funcArgsSizePerItem;
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template<typename CType>
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int
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getLaneOffset(int lane, int addr)
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{
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return addr * wfSize + sizeof(CType) * lane;
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}
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CallArgMem(int func_args_size_per_item, int wf_size)
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: wfSize(wf_size), funcArgsSizePerItem(func_args_size_per_item)
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{
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mem = (uint8_t*)malloc(funcArgsSizePerItem * wfSize);
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}
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~CallArgMem()
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{
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free(mem);
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}
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template<typename CType>
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uint8_t*
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getLaneAddr(int lane, int addr)
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{
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return mem + getLaneOffset<CType>(lane, addr);
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}
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template<typename CType>
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void
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setLaneAddr(int lane, int addr, CType val)
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{
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*((CType*)(mem + getLaneOffset<CType>(lane, addr))) = val;
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}
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};
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/**
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* A reconvergence stack entry conveys the necessary state to implement
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* control flow divergence.
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*/
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class ReconvergenceStackEntry {
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public:
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ReconvergenceStackEntry(uint32_t new_pc, uint32_t new_rpc,
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VectorMask new_mask) : pc(new_pc), rpc(new_rpc),
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execMask(new_mask) {
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}
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/**
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* PC of current instruction.
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*/
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uint32_t pc;
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/**
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* PC of the immediate post-dominator instruction, i.e., the value of
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* @a pc for the first instruction that will be executed by the wavefront
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* when a reconvergence point is reached.
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*/
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uint32_t rpc;
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/**
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* Execution mask.
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*/
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VectorMask execMask;
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};
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class Wavefront : public SimObject
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{
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public:
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enum itype_e {I_ALU,I_GLOBAL,I_SHARED,I_FLAT,I_PRIVATE};
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enum status_e {S_STOPPED,S_RETURNING,S_RUNNING};
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// Base pointer for array of instruction pointers
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uint64_t base_ptr;
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uint32_t old_barrier_cnt;
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uint32_t barrier_cnt;
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uint32_t barrier_id;
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uint32_t barrier_slots;
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status_e status;
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// HW slot id where the WF is mapped to inside a SIMD unit
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int wfSlotId;
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int kern_id;
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// SIMD unit where the WV has been scheduled
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int simdId;
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// pointer to parent CU
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ComputeUnit *computeUnit;
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std::deque<GPUDynInstPtr> instructionBuffer;
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bool pendingFetch;
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bool dropFetch;
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// Condition Register State (for HSAIL simulations only)
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class ConditionRegisterState *condRegState;
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// number of single precision VGPRs required by WF
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uint32_t maxSpVgprs;
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// number of double precision VGPRs required by WF
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uint32_t maxDpVgprs;
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// map virtual to physical vector register
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uint32_t remap(uint32_t vgprIndex, uint32_t size, uint8_t mode=0);
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void resizeRegFiles(int num_cregs, int num_sregs, int num_dregs);
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bool isGmInstruction(GPUDynInstPtr ii);
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bool isLmInstruction(GPUDynInstPtr ii);
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bool isOldestInstGMem();
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bool isOldestInstLMem();
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bool isOldestInstPrivMem();
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bool isOldestInstFlatMem();
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bool isOldestInstALU();
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bool isOldestInstBarrier();
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// used for passing spill address to DDInstGPU
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std::vector<Addr> last_addr;
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std::vector<uint32_t> workitemid[3];
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std::vector<uint32_t> workitemFlatId;
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uint32_t workgroupid[3];
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uint32_t workgroupsz[3];
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uint32_t gridsz[3];
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uint32_t wg_id;
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uint32_t wg_sz;
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uint32_t dynwaveid;
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uint32_t maxdynwaveid;
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uint32_t dispatchid;
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// outstanding global+local memory requests
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uint32_t outstanding_reqs;
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// memory requests between scoreboard
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// and execute stage not yet executed
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uint32_t mem_reqs_in_pipe;
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// outstanding global memory write requests
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uint32_t outstanding_reqs_wr_gm;
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// outstanding local memory write requests
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uint32_t outstanding_reqs_wr_lm;
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// outstanding global memory read requests
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uint32_t outstanding_reqs_rd_gm;
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// outstanding local memory read requests
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uint32_t outstanding_reqs_rd_lm;
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uint32_t rd_lm_reqs_in_pipe;
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uint32_t rd_gm_reqs_in_pipe;
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uint32_t wr_lm_reqs_in_pipe;
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uint32_t wr_gm_reqs_in_pipe;
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int mem_trace_busy;
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uint64_t last_trace;
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// number of vector registers reserved by WF
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int reservedVectorRegs;
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// Index into the Vector Register File's namespace where the WF's registers
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// will live while the WF is executed
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uint32_t startVgprIndex;
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// Old value of destination gpr (for trace)
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std::vector<uint32_t> old_vgpr;
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// Id of destination gpr (for trace)
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uint32_t old_vgpr_id;
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// Tick count of last old_vgpr copy
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uint64_t old_vgpr_tcnt;
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// Old value of destination gpr (for trace)
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std::vector<uint64_t> old_dgpr;
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// Id of destination gpr (for trace)
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uint32_t old_dgpr_id;
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// Tick count of last old_vgpr copy
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uint64_t old_dgpr_tcnt;
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// Execution mask at wavefront start
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VectorMask init_mask;
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// number of barriers this WF has joined
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std::vector<int> bar_cnt;
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int max_bar_cnt;
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// Flag to stall a wave on barrier
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bool stalledAtBarrier;
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// a pointer to the fraction of the LDS allocated
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// to this workgroup (thus this wavefront)
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LdsChunk *ldsChunk;
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// A pointer to the spill area
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Addr spillBase;
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// The size of the spill area
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uint32_t spillSizePerItem;
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// The vector width of the spill area
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uint32_t spillWidth;
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// A pointer to the private memory area
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Addr privBase;
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// The size of the private memory area
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uint32_t privSizePerItem;
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// A pointer ot the read-only memory area
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Addr roBase;
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// size of the read-only memory area
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uint32_t roSize;
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// pointer to buffer for storing kernel arguments
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uint8_t *kernelArgs;
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// unique WF id over all WFs executed across all CUs
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uint64_t wfDynId;
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// number of times instruction issue for this wavefront is blocked
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// due to VRF port availability
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Stats::Scalar numTimesBlockedDueVrfPortAvail;
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// number of times an instruction of a WF is blocked from being issued
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// due to WAR and WAW dependencies
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Stats::Scalar numTimesBlockedDueWAXDependencies;
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// number of times an instruction of a WF is blocked from being issued
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// due to WAR and WAW dependencies
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Stats::Scalar numTimesBlockedDueRAWDependencies;
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// distribution of executed instructions based on their register
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// operands; this is used to highlight the load on the VRF
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Stats::Distribution srcRegOpDist;
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Stats::Distribution dstRegOpDist;
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// Functions to operate on call argument memory
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// argument memory for hsail call instruction
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CallArgMem *callArgMem;
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void
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initCallArgMem(int func_args_size_per_item, int wf_size)
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{
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callArgMem = new CallArgMem(func_args_size_per_item, wf_size);
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}
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template<typename CType>
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CType
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readCallArgMem(int lane, int addr)
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{
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return *((CType*)(callArgMem->getLaneAddr<CType>(lane, addr)));
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}
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template<typename CType>
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void
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writeCallArgMem(int lane, int addr, CType val)
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{
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callArgMem->setLaneAddr<CType>(lane, addr, val);
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}
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typedef WavefrontParams Params;
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Wavefront(const Params *p);
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~Wavefront();
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virtual void init();
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void
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setParent(ComputeUnit *cu)
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{
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computeUnit = cu;
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}
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void start(uint64_t _wfDynId, uint64_t _base_ptr);
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void exec();
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void updateResources();
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int ready(itype_e type);
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bool instructionBufferHasBranch();
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void regStats();
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VectorMask get_pred() { return execMask() & init_mask; }
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bool waitingAtBarrier(int lane);
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void pushToReconvergenceStack(uint32_t pc, uint32_t rpc,
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const VectorMask& exec_mask);
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void popFromReconvergenceStack();
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uint32_t pc() const;
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uint32_t rpc() const;
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VectorMask execMask() const;
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bool execMask(int lane) const;
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void pc(uint32_t new_pc);
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void discardFetch();
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private:
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/**
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* Stack containing Control Flow Graph nodes (i.e., kernel instructions)
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* to be visited by the wavefront, and the associated execution masks. The
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* reconvergence stack grows every time the wavefront reaches a divergence
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* point (branch instruction), and shrinks every time the wavefront
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* reaches a reconvergence point (immediate post-dominator instruction).
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*/
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std::stack<std::unique_ptr<ReconvergenceStackEntry>> reconvergenceStack;
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};
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#endif // __WAVEFRONT_HH__
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