5f42bfcd56
- Add the option of redirecting stderr to a file. With the old behaviour, stderr would follow stdout if stdout was to a file, but stderr went to the host stderr if stdout went to the host stdout. The new default maintains stdout and stderr going to the host. Now the two can specify different files, but they will share a file descriptor if the name of the files is the same. - Add --output and --errout options to se.py to go with --input.
158 lines
5.5 KiB
Python
158 lines
5.5 KiB
Python
# Copyright (c) 2006-2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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# Simple test script
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#
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# "m5 test.py"
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import m5
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if m5.build_env['FULL_SYSTEM']:
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m5.panic("This script requires syscall emulation mode (*_SE).")
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from m5.objects import *
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import os, optparse, sys
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from os.path import join as joinpath
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m5.AddToPath('../common')
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import Simulation
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from Caches import *
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from cpu2000 import *
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# Get paths we might need. It's expected this file is in m5/configs/example.
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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parser = optparse.OptionParser()
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# Benchmark options
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parser.add_option("-c", "--cmd",
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default=joinpath(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
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help="The binary to run in syscall emulation mode.")
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parser.add_option("-o", "--options", default="",
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help='The options to pass to the binary, use " " around the entire string')
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parser.add_option("-i", "--input", default="", help="Read stdin from a file.")
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parser.add_option("--output", default="", help="Redirect stdout to a file.")
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parser.add_option("--errout", default="", help="Redirect stderr to a file.")
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execfile(os.path.join(config_root, "common", "Options.py"))
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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if options.bench:
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try:
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if m5.build_env['TARGET_ISA'] != 'alpha':
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print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time"
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sys.exit(1)
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exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
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process = workload.makeLiveProcess()
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except:
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print >>sys.stderr, "Unable to find workload for %s" % options.bench
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sys.exit(1)
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else:
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process = LiveProcess()
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process.executable = options.cmd
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process.cmd = [options.cmd] + options.options.split()
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if options.input != "":
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process.input = options.input
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if options.output != "":
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process.output = options.output
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if options.errout != "":
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process.errout = options.errout
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if options.detailed:
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#check for SMT workload
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workloads = options.cmd.split(';')
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if len(workloads) > 1:
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process = []
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smt_idx = 0
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inputs = []
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outputs = []
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errouts = []
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if options.input != "":
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inputs = options.input.split(';')
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if options.output != "":
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outputs = options.output.split(';')
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if options.errout != "":
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errouts = options.errout.split(';')
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for wrkld in workloads:
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smt_process = LiveProcess()
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smt_process.executable = wrkld
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smt_process.cmd = wrkld + " " + options.options
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if inputs and inputs[smt_idx]:
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smt_process.input = inputs[smt_idx]
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if outputs and outputs[smt_idx]:
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smt_process.output = outputs[smt_idx]
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if errouts and errouts[smt_idx]:
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smt_process.errout = errouts[smt_idx]
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process += [smt_process, ]
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smt_idx += 1
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(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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CPUClass.clock = '2GHz'
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np = options.num_cpus
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system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
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physmem = PhysicalMemory(range=AddrRange("512MB")),
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membus = Bus(), mem_mode = test_mem_mode)
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system.physmem.port = system.membus.port
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if options.l2cache:
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system.l2 = L2Cache(size='2MB')
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system.tol2bus = Bus()
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system.l2.cpu_side = system.tol2bus.port
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system.l2.mem_side = system.membus.port
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for i in xrange(np):
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if options.caches:
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system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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if options.l2cache:
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system.cpu[i].connectMemPorts(system.tol2bus)
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else:
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system.cpu[i].connectMemPorts(system.membus)
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system.cpu[i].workload = process
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if options.fastmem:
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system.cpu[0].physmem_port = system.physmem.port
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root = Root(system = system)
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Simulation.run(options, root, system, FutureClass)
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