968048f56a
InstObjParam interface. src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/fp.isa: src/arch/alpha/isa/int.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/isa/mem.isa: src/arch/alpha/isa/pal.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/util.isa: Get rid of CodeBlock calls to adapt to new InstObjParam interface. src/arch/isa_parser.py: Check template code for operands (in addition to snippets). src/cpu/o3/alpha/dyn_inst.hh: Add (read|write)MiscRegOperand calls to Alpha DynInst. --HG-- extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
133 lines
4.7 KiB
C++
133 lines
4.7 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Steve Reinhardt
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////////////////////////////////////////////////////////////////////
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//
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// Integer operate instructions
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//
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output header {{
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/**
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* Base class for integer immediate instructions.
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*/
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class IntegerImm : public AlphaStaticInst
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{
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protected:
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/// Immediate operand value (unsigned 8-bit int).
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uint8_t imm;
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/// Constructor
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IntegerImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
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: AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
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{
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// just print the first source reg... if there's
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// a second one, it's a read-modify-write dest (Rc),
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// e.g. for CMOVxx
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if (_numSrcRegs > 0) {
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printReg(ss, _srcRegIdx[0]);
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ss << ",";
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}
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ss << (int)imm;
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if (_numDestRegs > 0) {
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ss << ",";
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printReg(ss, _destRegIdx[0]);
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}
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return ss.str();
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}
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}};
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def template RegOrImmDecode {{
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{
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AlphaStaticInst *i =
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(IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
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: (AlphaStaticInst *)new %(class_name)s(machInst);
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if (RC == 31) {
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i = makeNop(i);
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}
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return i;
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}
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}};
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// Primary format for integer operate instructions:
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// - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
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// - Generates NOP if RC == 31.
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def format IntegerOperate(code, *opt_flags) {{
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# If the code block contains 'Rb_or_imm', we define two instructions,
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# one using 'Rb' and one using 'imm', and have the decoder select
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# the right one.
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uses_imm = (code.find('Rb_or_imm') != -1)
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if uses_imm:
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orig_code = code
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# base code is reg version:
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# rewrite by substituting 'Rb' for 'Rb_or_imm'
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code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
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# generate immediate version by substituting 'imm'
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# note that imm takes no extenstion, so we extend
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# the regexp to replace any extension as well
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imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
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# generate declaration for register version
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iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = BasicExecute.subst(iop)
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if uses_imm:
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# append declaration for imm version
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imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_code,
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opt_flags)
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header_output += BasicDeclare.subst(imm_iop)
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decoder_output += BasicConstructor.subst(imm_iop)
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exec_output += BasicExecute.subst(imm_iop)
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# decode checks IMM bit to pick correct version
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decode_block = RegOrImmDecode.subst(iop)
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else:
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# no imm version: just check for nop
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decode_block = OperateNopCheckDecode.subst(iop)
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}};
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