Andreas Hansson 36dc93a5fa mem: Move crossbar default latencies to subclasses ... This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden.		2015-03-02 04:00:47 -05:00
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Benchmarks.py	config: add --root-device machine parameter	2015-01-16 14:12:03 -06:00
CacheConfig.py	mem: Move crossbar default latencies to subclasses	2015-03-02 04:00:47 -05:00
Caches.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
cpu2000.py	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
CpuConfig.py	scons: Do not build the InOrderCPU	2015-01-20 08:12:45 -05:00
FSConfig.py	mem: Move crossbar default latencies to subclasses	2015-03-02 04:00:47 -05:00
MemConfig.py	config: Add XOR hashing to the DRAM channel interleaving	2015-02-03 14:25:55 -05:00
O3_ARM_v7a.py	cpu: Change writeback modeling for outstanding instructions	2014-09-03 07:42:33 -04:00
Options.py	config: add --root-device machine parameter	2015-01-16 14:12:03 -06:00
Simulation.py	config: Add options to take/resume from SimPoint checkpoints	2014-12-23 09:31:17 -05:00
SysPaths.py	config: rename 'file' var	2015-02-05 16:45:12 -08:00