d3aebe1f91
The patch started of with replacing Time with Cycles in the Consumer class. But to get ruby to compile, the rest of the changes had to be carried out. Subsequent patches will further this process, till we completely replace Time with Cycles.
67 lines
2.5 KiB
C++
67 lines
2.5 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Common base class for a machine node.
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*/
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#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
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#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
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#include <iostream>
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#include "mem/protocol/AccessPermission.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Global.hh"
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#include "mem/ruby/slicc_interface/AbstractEntry.hh"
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class DataBlock;
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class AbstractCacheEntry : public AbstractEntry
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{
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public:
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AbstractCacheEntry();
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virtual ~AbstractCacheEntry() = 0;
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// Get/Set permission of the entry
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void changePermission(AccessPermission new_perm);
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Address m_Address; // Address of this block, required by CacheMemory
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int m_locked; // Holds info whether the address is locked,
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// required for implementing LL/SC
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};
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inline std::ostream&
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operator<<(std::ostream& out, const AbstractCacheEntry& obj)
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{
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obj.print(out);
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out << std::flush;
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return out;
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}
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#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
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