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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
Andreas Hansson b387d8e213 stats: Update the stats to reflect the 1GHz default system clock 
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
2012-10-25 13:15:59 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.603636 # Number of seconds simulated
sim_ticks 2603636076000 # Number of ticks simulated
final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 264193 # Simulator instruction rate (inst/s)
host_op_rate 336182 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 11426847777 # Simulator tick rate (ticks/s)
host_mem_usage 395692 # Number of bytes of host memory used
host_seconds 227.85 # Real time elapsed on the host
sim_insts 60197128 # Number of instructions simulated
sim_ops 76599899 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory
system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47120023 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 270698 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3475957 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50866875 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 270698 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 270698 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1412449 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2570857 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1412449 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47120023 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 270698 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4634365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53437732 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15494089 # Total number of read requests seen
system.physmem.writeReqs 811479 # Total number of write requests seen
system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 991621696 # Total number of bytes read from memory
system.physmem.bytesWritten 51934656 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 967593 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 967789 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 50620 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51037 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 2603631716000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6652 # Categorize read packet sizes
system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 152013 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 754018 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 57461 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 15419657 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 56436 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 11795 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2249 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1058 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 797 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 386 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 213 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 117 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 85 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 73 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 46 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 35279 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 3750171610 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 281910621610 # Sum of mem lat for all requests
system.physmem.totBusLat 61975012000 # Total cycles spent in databus access
system.physmem.totBankLat 216185438000 # Total cycles spent in bank access
system.physmem.avgQLat 242.04 # Average queueing delay per request
system.physmem.avgBankLat 13953.07 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 18195.12 # Average memory access latency
system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.51 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.11 # Average read queue length over time
system.physmem.avgWrQLen 12.38 # Average write queue length over time
system.physmem.readRowHits 15449450 # Number of row buffer hits during reads
system.physmem.writeRowHits 784611 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes
system.physmem.avgGap 159677.46 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 14995523 # DTB read hits
system.cpu.dtb.read_misses 7332 # DTB read misses
system.cpu.dtb.write_hits 11230789 # DTB write hits
system.cpu.dtb.write_misses 2203 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 15002855 # DTB read accesses
system.cpu.dtb.write_accesses 11232992 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 26226312 # DTB hits
system.cpu.dtb.misses 9535 # DTB misses
system.cpu.dtb.accesses 26235847 # DTB accesses
system.cpu.itb.inst_hits 61491068 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 61495539 # ITB inst accesses
system.cpu.itb.hits 61491068 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 61495539 # DTB accesses
system.cpu.numCycles 5207272152 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 60197128 # Number of instructions committed
system.cpu.committedOps 76599899 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 68867725 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 2139710 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7947746 # number of instructions that are conditional controls
system.cpu.num_int_insts 68867725 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read
system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27393681 # number of memory refs
system.cpu.num_load_insts 15659530 # Number of load instructions
system.cpu.num_store_insts 11734151 # Number of store instructions
system.cpu.num_idle_cycles 4579080256.576241 # Number of idle cycles
system.cpu.num_busy_cycles 628191895.423759 # Number of busy cycles
system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.879363 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed
system.cpu.icache.replacements 855500 # number of replacements
system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use
system.cpu.icache.total_refs 60635056 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 856012 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70.834353 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 60635056 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60635056 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60635056 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60635056 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60635056 # number of overall hits
system.cpu.icache.overall_hits::total 60635056 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 856012 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 856012 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 856012 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 856012 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 856012 # number of overall misses
system.cpu.icache.overall_misses::total 856012 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11543876000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11543876000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11543876000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11543876000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11543876000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11543876000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61491068 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61491068 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61491068 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11485.647397 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency
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system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 536335000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6619354500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 7156114000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8707 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 854387 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 380163 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1246808 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 596013 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 596013 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247604 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247604 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8707 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 854387 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 627767 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1494412 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8707 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 854387 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 627767 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1494412 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012405 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025931 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537899 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.537899 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012405 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.227862 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.102817 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012405 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.227862 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.102817 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 57500 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 45666.666667 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50602.415322 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52443.396226 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51490.178353 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.167131 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.167131 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45818.385566 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45818.385566 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 46573.819891 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 46573.819891 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 57461 # number of writebacks
system.cpu.l2cache.writebacks::total 57461 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 20465 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 143044 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 153651 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143044 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 153651 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 224010 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 98006 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 398671075 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 388940100 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 787933191 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28807316 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28807316 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4371975723 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4371975723 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 224010 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 98006 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 398671075 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4760915823 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5159908914 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 224010 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 98006 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 398671075 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4760915823 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5159908914 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 197466551 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166694484565 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166891951116 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175103106 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175103106 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175869587671 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176067054222 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025931 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537899 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537899 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.102817 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37614.027267 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39454.260499 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38501.499682 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.402507 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.402507 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32826.090753 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32826.090753 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1052665426345 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1052665426345 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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