323 lines
9.8 KiB
C++
323 lines
9.8 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2007 MIPS Technologies, Inc.
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Korey Sewell
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////////////////////////////////////////////////////////////////////
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//
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// Control transfer instructions
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//
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output header {{
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#include <iostream>
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using namespace std;
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/**
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* Base class for instructions whose disassembly is not purely a
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* function of the machine instruction (i.e., it depends on the
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* PC). This class overrides the disassemble() method to check
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* the PC and symbol table values before re-using a cached
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* disassembly string. This is necessary for branches and jumps,
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* where the disassembly string includes the target address (which
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* may depend on the PC and/or symbol table).
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*/
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class PCDependentDisassembly : public MipsStaticInst
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{
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protected:
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/// Cached program counter from last disassembly
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mutable Addr cachedPC;
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/// Cached symbol table pointer from last disassembly
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mutable const SymbolTable *cachedSymtab;
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/// Constructor
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PCDependentDisassembly(const char *mnem, MachInst _machInst,
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OpClass __opClass)
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: MipsStaticInst(mnem, _machInst, __opClass),
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cachedPC(0), cachedSymtab(0)
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{
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}
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const std::string &
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disassemble(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for branches (PC-relative control transfers),
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* conditional or unconditional.
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*/
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class Branch : public PCDependentDisassembly
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{
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protected:
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/// target address (signed) Displacement .
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int32_t disp;
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/// Constructor.
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Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(OFFSET << 2)
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{
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//If Bit 17 is 1 then Sign Extend
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if ( (disp & 0x00020000) > 0 ) {
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disp |= 0xFFFE0000;
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}
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}
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Addr branchTarget(Addr branchPC) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for jumps (register-indirect control transfers). In
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* the Mips ISA, these are always unconditional.
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*/
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class Jump : public PCDependentDisassembly
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{
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protected:
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/// Displacement to target address (signed).
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int32_t disp;
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uint32_t target;
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public:
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/// Constructor
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Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(JMPTARG << 2)
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{
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}
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Addr branchTarget(ThreadContext *tc) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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Addr
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Branch::branchTarget(Addr branchPC) const
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{
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return branchPC + 4 + disp;
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}
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Addr
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Jump::branchTarget(ThreadContext *tc) const
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{
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Addr NPC = tc->readNextPC();
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return (NPC & 0xF0000000) | (disp);
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}
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const std::string &
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PCDependentDisassembly::disassemble(Addr pc,
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const SymbolTable *symtab) const
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{
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if (!cachedDisassembly ||
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pc != cachedPC || symtab != cachedSymtab)
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{
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if (cachedDisassembly)
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delete cachedDisassembly;
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cachedDisassembly =
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new std::string(generateDisassembly(pc, symtab));
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cachedPC = pc;
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cachedSymtab = symtab;
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}
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return *cachedDisassembly;
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}
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std::string
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Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// There's only one register arg (RA), but it could be
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// either a source (the condition for conditional
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// branches) or a destination (the link reg for
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// unconditional branches)
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if (_numSrcRegs == 1) {
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printReg(ss, _srcRegIdx[0]);
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ss << ", ";
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} else if(_numSrcRegs == 2) {
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printReg(ss, _srcRegIdx[0]);
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ss << ", ";
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printReg(ss, _srcRegIdx[1]);
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ss << ", ";
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}
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Addr target = pc + 4 + disp;
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std::string str;
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if (symtab && symtab->findSymbol(target, str))
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ss << str;
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else
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ccprintf(ss, "0x%x", target);
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return ss.str();
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}
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std::string
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Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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if ( strcmp(mnemonic,"jal") == 0 ) {
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Addr npc = pc + 4;
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ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
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} else if (_numSrcRegs == 0) {
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std::string str;
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if (symtab && symtab->findSymbol(disp, str))
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ss << str;
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else
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ccprintf(ss, "0x%x", disp);
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} else if (_numSrcRegs == 1) {
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printReg(ss, _srcRegIdx[0]);
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} else if(_numSrcRegs == 2) {
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printReg(ss, _srcRegIdx[0]);
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ss << ", ";
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printReg(ss, _srcRegIdx[1]);
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}
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return ss.str();
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}
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}};
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def format Branch(code, *opt_flags) {{
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not_taken_code = ' NNPC = NNPC;\n'
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not_taken_code += '} \n'
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#Build Instruction Flags
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#Use Link & Likely Flags to Add Link/Condition Code
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inst_flags = ('IsDirectControl', )
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for x in opt_flags:
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if x == 'Link':
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code += 'R31 = NNPC;\n'
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elif x == 'Likely':
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not_taken_code = ' NPC = NNPC;\n'
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not_taken_code += ' NNPC = NNPC + 4;\n'
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not_taken_code += '} \n'
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inst_flags += ('IsCondDelaySlot', )
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else:
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inst_flags += (x, )
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#Take into account uncond. branch instruction
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if 'cond = 1' in code:
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inst_flags += ('IsUncondControl', )
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else:
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inst_flags += ('IsCondControl', )
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#Condition code
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code = 'bool cond;\n' + code
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code += 'if (cond) {\n'
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code += ' NNPC = NPC + disp;\n'
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code += '} else {\n'
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code += not_taken_code
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iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format DspBranch(code, *opt_flags) {{
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not_taken_code = ' NNPC = NNPC;\n'
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not_taken_code += '} \n'
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#Build Instruction Flags
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#Use Link & Likely Flags to Add Link/Condition Code
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inst_flags = ('IsDirectControl', )
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for x in opt_flags:
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if x == 'Link':
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code += 'R31 = NNPC;\n'
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elif x == 'Likely':
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not_taken_code = ' NPC = NNPC;\n'
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not_taken_code += ' NNPC = NNPC + 4;\n'
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not_taken_code += '} \n'
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inst_flags += ('IsCondDelaySlot', )
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else:
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inst_flags += (x, )
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#Take into account uncond. branch instruction
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if 'cond = 1' in code:
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inst_flags += ('IsUncondControl', )
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else:
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inst_flags += ('IsCondControl', )
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#Declaration code
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decl_code = 'bool cond;\n'
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decl_code += 'uint32_t dspctl;\n'
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#Fetch code
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fetch_code = 'dspctl = DSPControl;\n'
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#Condition code
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code = decl_code + fetch_code + code
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code += 'if (cond) {\n'
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code += ' NNPC = NPC + disp;\n'
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code += '} else {\n'
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code += not_taken_code
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iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format Jump(code, *opt_flags) {{
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#Build Instruction Flags
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#Use Link Flag to Add Link Code
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inst_flags = ('IsIndirectControl', 'IsUncondControl')
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for x in opt_flags:
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if x == 'Link':
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code = 'R31 = NNPC;\n' + code
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elif x == 'ClearHazards':
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code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
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else:
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inst_flags += (x, )
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iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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