040fa23d01
Only printing one rather than two args for the ignored syscall warning means the count of register accesses has changed on a few runs. Oddly only Alpha Tru64 seems to have any ignored syscalls in the regression tests.
1016 lines
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1016 lines
116 KiB
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.679350 # Number of seconds simulated
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sim_ticks 679349778000 # Number of ticks simulated
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final_tick 679349778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 176355 # Simulator instruction rate (inst/s)
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host_op_rate 176355 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 69011357 # Simulator tick rate (ticks/s)
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host_mem_usage 223060 # Number of bytes of host memory used
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host_seconds 9844.03 # Real time elapsed on the host
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sim_insts 1736043781 # Number of instructions simulated
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sim_ops 1736043781 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 125814720 # Number of bytes read from this memory
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system.physmem.bytes_read::total 125876544 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 65265856 # Number of bytes written to this memory
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system.physmem.bytes_written::total 65265856 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1965855 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1966821 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1019779 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1019779 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 91005 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 185198736 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 185289740 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 91005 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 91005 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 96071064 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 96071064 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 96071064 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 91005 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 185198736 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 281360804 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 1966821 # Number of read requests accepted
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system.physmem.writeReqs 1019779 # Number of write requests accepted
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system.physmem.readBursts 1966821 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1019779 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 125795136 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 81408 # Total number of bytes read from write queue
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system.physmem.bytesWritten 65264000 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 125876544 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 65265856 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 1272 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 118990 # Per bank write bursts
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system.physmem.perBankRdBursts::1 114401 # Per bank write bursts
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system.physmem.perBankRdBursts::2 116526 # Per bank write bursts
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system.physmem.perBankRdBursts::3 118038 # Per bank write bursts
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system.physmem.perBankRdBursts::4 118100 # Per bank write bursts
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system.physmem.perBankRdBursts::5 117781 # Per bank write bursts
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system.physmem.perBankRdBursts::6 120191 # Per bank write bursts
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system.physmem.perBankRdBursts::7 124916 # Per bank write bursts
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system.physmem.perBankRdBursts::8 127523 # Per bank write bursts
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system.physmem.perBankRdBursts::9 130444 # Per bank write bursts
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system.physmem.perBankRdBursts::10 129055 # Per bank write bursts
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system.physmem.perBankRdBursts::11 130769 # Per bank write bursts
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system.physmem.perBankRdBursts::12 126629 # Per bank write bursts
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system.physmem.perBankRdBursts::13 125625 # Per bank write bursts
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system.physmem.perBankRdBursts::14 122929 # Per bank write bursts
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system.physmem.perBankRdBursts::15 123632 # Per bank write bursts
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system.physmem.perBankWrBursts::0 61276 # Per bank write bursts
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system.physmem.perBankWrBursts::1 61573 # Per bank write bursts
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system.physmem.perBankWrBursts::2 60655 # Per bank write bursts
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system.physmem.perBankWrBursts::3 61329 # Per bank write bursts
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system.physmem.perBankWrBursts::4 61751 # Per bank write bursts
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system.physmem.perBankWrBursts::5 63183 # Per bank write bursts
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system.physmem.perBankWrBursts::6 64216 # Per bank write bursts
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system.physmem.perBankWrBursts::7 65714 # Per bank write bursts
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system.physmem.perBankWrBursts::8 65484 # Per bank write bursts
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system.physmem.perBankWrBursts::9 65866 # Per bank write bursts
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system.physmem.perBankWrBursts::10 65407 # Per bank write bursts
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system.physmem.perBankWrBursts::11 65735 # Per bank write bursts
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system.physmem.perBankWrBursts::12 64310 # Per bank write bursts
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system.physmem.perBankWrBursts::13 64307 # Per bank write bursts
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system.physmem.perBankWrBursts::14 64646 # Per bank write bursts
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system.physmem.perBankWrBursts::15 64298 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 679349688500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 1966821 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1019779 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1643770 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 225726 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 72200 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 23834 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 28029 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 29643 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 50000 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 56258 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 59169 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 60158 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 60388 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 60609 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 60716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 61035 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 61226 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 61677 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 63137 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 63948 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 61422 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 62019 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 60448 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 59666 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 135 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 37 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1771721 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 107.836103 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 82.953832 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 137.029832 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 1375665 77.65% 77.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 272762 15.40% 93.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 53440 3.02% 96.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 21316 1.20% 97.26% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 12827 0.72% 97.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 6576 0.37% 98.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 5044 0.28% 98.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 3861 0.22% 98.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 20230 1.14% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1771721 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 59588 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 32.942421 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 164.012858 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 59550 99.94% 99.94% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-3071 13 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 59588 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 59588 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.113345 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 17.071670 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.230173 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-17 30977 51.99% 51.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18-19 27509 46.17% 98.15% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20-21 1030 1.73% 99.88% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22-23 43 0.07% 99.95% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::26-27 4 0.01% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::30-31 11 0.02% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::32-33 1 0.00% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::42-43 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::76-77 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 59588 # Writes before turning the bus around for reads
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system.physmem.totQLat 40014194750 # Total ticks spent queuing
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system.physmem.totMemAccLat 76868238500 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 9827745000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 20357.77 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 39107.77 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 185.17 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 96.07 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 185.29 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 96.07 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 2.20 # Data bus utilization in percentage
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system.physmem.busUtilRead 1.45 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 25.15 # Average write queue length when enqueuing
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system.physmem.readRowHits 795833 # Number of row buffer hits during reads
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system.physmem.writeRowHits 417735 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 40.49 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 40.96 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 227465.91 # Average gap between requests
|
|
system.physmem.pageHitRate 40.65 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 134374460000 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 22684740000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 522286376500 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.membus.throughput 281360804 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 1191893 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 1191893 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 1019779 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 774928 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 774928 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4953421 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 4953421 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191142400 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 191142400 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 191142400 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 11809306000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 18437139750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 2.7 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 390516660 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 303583970 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 16113462 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 268537122 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 266026822 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 99.065194 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 25282995 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 3069 # Number of incorrect RAS predictions.
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 621222786 # DTB read hits
|
|
system.cpu.dtb.read_misses 11503040 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 632725826 # DTB read accesses
|
|
system.cpu.dtb.write_hits 213831979 # DTB write hits
|
|
system.cpu.dtb.write_misses 7254265 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 221086244 # DTB write accesses
|
|
system.cpu.dtb.data_hits 835054765 # DTB hits
|
|
system.cpu.dtb.data_misses 18757305 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 853812070 # DTB accesses
|
|
system.cpu.itb.fetch_hits 400046189 # ITB hits
|
|
system.cpu.itb.fetch_misses 44 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 400046233 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 29 # Number of system calls
|
|
system.cpu.numCycles 1358699557 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 410929991 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 3243314345 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 390516660 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 291309817 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 589336372 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 147340013 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 133548447 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 1456 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 400046189 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 9025513 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 1257254668 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.579680 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.173136 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 667918296 53.13% 53.13% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 44267394 3.52% 56.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 22207289 1.77% 58.41% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 40636739 3.23% 61.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 131869370 10.49% 72.13% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 62966774 5.01% 77.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 40227274 3.20% 80.34% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 28245094 2.25% 82.59% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 218916438 17.41% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 1257254668 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.287419 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.387072 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 430550615 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 129659255 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 568815009 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 4792365 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 123437424 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 59500767 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 917 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 3153748807 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 2128 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 123437424 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 446386402 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 61779163 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 6860 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 557518816 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 68126003 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 3069486898 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 1505727 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 6123879 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 54202488 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 8466199 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 2295837862 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 3983545178 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 3983398130 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 147047 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 919634899 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 203 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 202 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 44876150 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 692163471 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 260495859 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 73383628 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 38808502 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2780183806 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 184 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2536585762 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 4364880 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 1034533664 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 460650584 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 155 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 1257254668 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.017559 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.009997 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 428157011 34.05% 34.05% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 188380197 14.98% 49.04% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 177998596 14.16% 63.20% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 153960413 12.25% 75.44% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 135215337 10.75% 86.20% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 80818226 6.43% 92.62% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 69593138 5.54% 98.16% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 17238172 1.37% 99.53% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 5893578 0.47% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 1257254668 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 2760636 13.79% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 12853797 64.19% 77.98% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 4410220 22.02% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1663143410 65.57% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 259 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 21 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 647516942 25.53% 91.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 225924828 8.91% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2536585762 # Type of FU issued
|
|
system.cpu.iq.rate 1.866922 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 20024653 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.007894 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 6352883505 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 3813585390 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2440929650 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 1932220 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 1252073 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 864209 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2555655812 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 954603 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 64558247 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 247567808 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 343004 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 121628 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 99767357 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 225 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 1607198 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 123437424 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 22713536 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 8297734 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 2923674181 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 8955846 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 692163471 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 260495859 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 184 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 449856 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 8304684 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 121628 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 10428435 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 8597760 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 19026195 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2492121408 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 632726353 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 44464354 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 143490191 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 853812632 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 304222027 # Number of branches executed
|
|
system.cpu.iew.exec_stores 221086279 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.834196 # Inst execution rate
|
|
system.cpu.iew.wb_sent 2470047897 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 2441793859 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1422096892 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1830175974 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.797155 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.777027 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 873443731 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 16112643 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1133817244 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.605003 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.541695 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 625261340 55.15% 55.15% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 171314027 15.11% 70.26% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 86268180 7.61% 77.86% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 54871559 4.84% 82.70% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 31288205 2.76% 85.46% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 20767631 1.83% 87.30% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 23576751 2.08% 89.37% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 22892827 2.02% 91.39% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 97576724 8.61% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1133817244 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 605324165 # Number of memory references committed
|
|
system.cpu.commit.loads 444595663 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 214632552 # Number of branches committed
|
|
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 1130719227 62.13% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 75 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 166 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 97576724 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 3643685177 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 5509997541 # The number of ROB writes
|
|
system.cpu.timesIdled 1119552 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 101444889 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.782641 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.782641 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.277725 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.277725 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 3354502670 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1955490145 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 31250 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 519 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 1216162152 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 7299986 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 7299986 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 3725797 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1883584 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1883584 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22091005 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 22092937 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826137664 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 826199488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 826199488 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 10180553427 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1609000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 14076007750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 1 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 775.530288 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 400044658 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 966 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 414124.904762 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 775.530288 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.378677 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.378677 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 912 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 800093342 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 800093342 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 400044658 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 400044658 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 400044658 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 400044658 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 400044658 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 400044658 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1530 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1530 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1530 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1530 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1530 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1530 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 107584749 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 107584749 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 107584749 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 107584749 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 107584749 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 107584749 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 400046188 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 400046188 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 400046188 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 400046188 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 400046188 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 400046188 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70316.829412 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 70316.829412 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70316.829412 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 70316.829412 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70316.829412 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 70316.829412 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 293 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 48.833333 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 564 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 564 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 564 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 564 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 564 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 564 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73366499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 73366499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73366499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 73366499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73366499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 73366499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75948.756729 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75948.756729 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75948.756729 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 75948.756729 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75948.756729 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 75948.756729 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 1934120 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 31423.856311 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 9061358 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 1963896 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 4.613970 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 28109033750 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 14558.709173 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.630498 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 16838.516639 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.444297 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000813 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.513871 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.958980 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 973 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 595 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17352 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10703 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 107122416 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 107122416 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 6108093 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 6108093 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 3725797 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 3725797 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1108656 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1108656 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7216749 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7216749 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7216749 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7216749 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 966 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1190927 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1191893 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 774928 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 774928 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 966 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1965855 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1966821 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 966 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1965855 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1966821 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 72391000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 97891621750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 97964012750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63926223998 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 63926223998 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 72391000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 161817845748 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 161890236748 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 72391000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 161817845748 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 161890236748 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 966 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 7299020 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7299986 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 3725797 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 3725797 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883584 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1883584 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 966 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9182604 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9183570 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 966 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9182604 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9183570 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163163 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.163273 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411411 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.411411 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214085 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.214167 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214085 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.214167 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74938.923395 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82197.835594 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 82191.952424 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82493.114196 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82493.114196 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74938.923395 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82314.232610 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 82310.610243 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74938.923395 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82314.232610 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 82310.610243 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1019779 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1019779 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190927 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1191893 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 774928 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 774928 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1965855 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 1966821 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1965855 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 1966821 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 60233500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 82944620750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83004854250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54243912498 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54243912498 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 60233500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137188533248 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 137248766748 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 60233500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137188533248 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 137248766748 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163163 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163273 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411411 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411411 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214085 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214167 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214085 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214167 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62353.519669 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69647.107463 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69641.196190 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69998.648259 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69998.648259 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62353.519669 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69785.682692 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69782.032401 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62353.519669 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69785.682692 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69782.032401 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 9178508 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4087.552800 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 699314315 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 9182604 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 76.156427 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 5143328250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.552800 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.997938 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.997938 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 755 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2929 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1441348176 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1441348176 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 543788004 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 543788004 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 155526308 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 155526308 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 699314312 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 699314312 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 699314312 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 699314312 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 11566276 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 11566276 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 5202194 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 5202194 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 16768470 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 16768470 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 16768470 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 16768470 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 334833749250 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 334833749250 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 287624135124 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 287624135124 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 622457884374 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 622457884374 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 622457884374 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 622457884374 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 555354280 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 555354280 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 716082782 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 716082782 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 716082782 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 716082782 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020827 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.020827 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032366 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.032366 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.023417 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.023417 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.023417 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.023417 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28949.140523 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 28949.140523 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55289.005970 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 55289.005970 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37120.732206 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 37120.732206 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37120.732206 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 37120.732206 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 11998793 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 8384809 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 779484 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 65137 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.393251 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 128.725747 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 3725797 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 3725797 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4267247 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 4267247 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3318620 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3318620 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 7585867 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 7585867 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 7585867 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 7585867 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7299029 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7299029 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883574 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1883574 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9182603 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 9182603 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9182603 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9182603 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 167129067750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 167129067750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77336919371 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 77336919371 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244465987121 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 244465987121 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244465987121 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 244465987121 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013143 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013143 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012823 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.012823 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012823 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.012823 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22897.438515 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22897.438515 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41058.604213 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41058.604213 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26622.732914 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26622.732914 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26622.732914 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26622.732914 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|