35147170f9
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
86 lines
3.1 KiB
Python
Executable file
86 lines
3.1 KiB
Python
Executable file
# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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import sys
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Import('*')
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if 'O3CPU' in env['CPU_MODELS']:
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SimObject('FUPool.py')
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SimObject('FuncUnitConfig.py')
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SimObject('O3CPU.py')
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Source('base_dyn_inst.cc')
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Source('bpred_unit.cc')
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Source('commit.cc')
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Source('cpu.cc')
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Source('decode.cc')
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Source('fetch.cc')
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Source('free_list.cc')
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Source('fu_pool.cc')
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Source('iew.cc')
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Source('inst_queue.cc')
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Source('lsq.cc')
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Source('lsq_unit.cc')
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Source('mem_dep_unit.cc')
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Source('rename.cc')
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Source('rename_map.cc')
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Source('rob.cc')
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Source('scoreboard.cc')
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Source('store_set.cc')
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if env['TARGET_ISA'] == 'alpha':
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Source('alpha/cpu.cc')
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Source('alpha/cpu_builder.cc')
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Source('alpha/dyn_inst.cc')
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Source('alpha/thread_context.cc')
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elif env['TARGET_ISA'] == 'mips':
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Source('mips/cpu.cc')
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Source('mips/cpu_builder.cc')
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Source('mips/dyn_inst.cc')
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Source('mips/thread_context.cc')
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elif env['TARGET_ISA'] == 'sparc':
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Source('sparc/cpu.cc')
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Source('sparc/cpu_builder.cc')
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Source('sparc/dyn_inst.cc')
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Source('sparc/thread_context.cc')
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else:
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sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
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if env['USE_CHECKER']:
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SimObject('m5/objects/O3Checker.py')
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Source('checker_builder.cc')
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if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
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Source('2bit_local_pred.cc')
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Source('btb.cc')
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Source('ras.cc')
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Source('tournament_pred.cc')
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