5a9a743cfc
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
113 lines
3.7 KiB
Python
113 lines
3.7 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Brad Beckmann
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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# Get paths we might need. It's expected this file is in m5/configs/example.
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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import Ruby
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parser = optparse.OptionParser()
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#
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# Add the ruby specific and protocol specific options
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#
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Ruby.define_options(parser)
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execfile(os.path.join(config_root, "configs/common", "Options.py"))
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(options, args) = parser.parse_args()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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options.l1d_size="256B"
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options.l1i_size="256B"
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options.l2_size="512B"
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options.l3_size="1kB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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#
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# create the tester and system, including ruby
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#
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tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10)
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system = System(tester = tester, physmem = PhysicalMemory())
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Ruby.create_system(options, system)
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assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
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#
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# The tester is most effective when randomization is turned on and
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# artifical delay is randomly inserted on messages
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#
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system.ruby.randomization = True
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for ruby_port in system.ruby._cpu_ruby_ports:
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#
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# Tie the ruby tester ports to the ruby cpu ports
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#
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tester.cpuPort = ruby_port.slave
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#
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# Tell the sequencer this is the ruby tester so that it
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# copies the subblock back to the checker
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#
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ruby_port.using_ruby_tester = True
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#
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# Ruby doesn't need the backing image of memory when running with
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# the tester.
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#
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ruby_port.access_phys_mem = False
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# -----------------------
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# run simulation
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# -----------------------
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root = Root(full_system = False, system = system )
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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