33b28fde7a
This changeset contains a lot of different changes that are too mingled to separate. They are: 1. Added MOESI_CMP_directory I made the changes necessary to bring back MOESI_CMP_directory, including adding a DMA controller. I got rid of MOESI_CMP_directory_m and made MOESI_CMP_directory use a memory controller. Added a new configuration for two level protocols in general, and MOESI_CMP_directory in particular. 2. DMA Sequencer uses a generic SequencerMsg I will eventually make the cache Sequencer use this type as well. It doesn't contain an offset field, just a physical address and a length. MI_example has been updated to deal with this. 3. Parameterized Controllers SLICC controllers can now take custom parameters to use for mapping, latencies, etc. Currently, only int parameters are supported.
607 lines
19 KiB
Text
607 lines
19 KiB
Text
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machine(Directory, "Directory protocol")
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: int directory_latency
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{
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MessageBuffer forwardFromDir, network="To", virtual_network="2", ordered="false";
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MessageBuffer responseFromDir, network="To", virtual_network="1", ordered="false";
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MessageBuffer dmaRequestFromDir, network="To", virtual_network="4", ordered="true";
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MessageBuffer requestToDir, network="From", virtual_network="0", ordered="true";
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MessageBuffer dmaRequestToDir, network="From", virtual_network="5", ordered="true";
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// STATES
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enumeration(State, desc="Directory states", default="Directory_State_I") {
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// Base states
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I, desc="Invalid";
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M, desc="Modified";
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M_DRD, desc="Blocked on an invalidation for a DMA read";
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M_DWR, desc="Blocked on an invalidation for a DMA write";
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M_DWRI, desc="Intermediate state M_DWR-->I";
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IM, desc="Intermediate state I-->M";
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MI, desc="Intermediate state M-->I";
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ID, desc="Intermediate state for DMA_READ when in I";
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ID_W, desc="Intermediate state for DMA_WRITE when in I";
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}
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// Events
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enumeration(Event, desc="Directory events") {
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// processor requests
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GETX, desc="A GETX arrives";
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GETS, desc="A GETS arrives";
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PUTX, desc="A PUTX arrives";
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PUTX_NotOwner, desc="A PUTX arrives";
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// DMA requests
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DMA_READ, desc="A DMA Read memory request";
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DMA_WRITE, desc="A DMA Write memory request";
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// Memory Controller
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Memory_Data, desc="Fetched data from memory arrives";
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Memory_Ack, desc="Writeback Ack from memory arrives";
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}
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// TYPES
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// DirectoryEntry
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structure(Entry, desc="...") {
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State DirectoryState, desc="Directory state";
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DataBlock DataBlk, desc="data for the block";
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NetDest Sharers, desc="Sharers for this block";
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NetDest Owner, desc="Owner of this block";
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}
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external_type(DirectoryMemory) {
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Entry lookup(Address);
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bool isPresent(Address);
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void invalidateBlock(Address);
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}
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external_type(MemoryControl, inport="yes", outport="yes") {
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}
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// TBE entries for DMA requests
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structure(TBE, desc="TBE entries for outstanding DMA requests") {
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Address PhysicalAddress, desc="physical address";
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State TBEState, desc="Transient State";
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DataBlock DataBlk, desc="Data to be written (DMA write only)";
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int Len, desc="...";
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}
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external_type(TBETable) {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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// ** OBJECTS **
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DirectoryMemory directory, factory='RubySystem::getDirectory(m_cfg["directory_name"])';
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MemoryControl memBuffer, factory='RubySystem::getMemoryControl(m_cfg["memory_controller_name"])';
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TBETable TBEs, template_hack="<Directory_TBE>";
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State getState(Address addr) {
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if (TBEs.isPresent(addr)) {
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return TBEs[addr].TBEState;
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} else if (directory.isPresent(addr)) {
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return directory[addr].DirectoryState;
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} else {
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return State:I;
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}
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}
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void setState(Address addr, State state) {
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if (TBEs.isPresent(addr)) {
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TBEs[addr].TBEState := state;
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}
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if (directory.isPresent(addr)) {
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if (state == State:I) {
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assert(directory[addr].Owner.count() == 0);
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assert(directory[addr].Sharers.count() == 0);
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} else if (state == State:M) {
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assert(directory[addr].Owner.count() == 1);
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assert(directory[addr].Sharers.count() == 0);
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}
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directory[addr].DirectoryState := state;
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}
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}
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// ** OUT_PORTS **
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out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
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out_port(responseNetwork_out, ResponseMsg, responseFromDir);
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out_port(requestQueue_out, ResponseMsg, requestToDir); // For recycling requests
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out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaRequestFromDir);
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//added by SS
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out_port(memQueue_out, MemoryMsg, memBuffer);
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// ** IN_PORTS **
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in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
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if (dmaRequestQueue_in.isReady()) {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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if (in_msg.Type == DMARequestType:READ) {
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trigger(Event:DMA_READ, in_msg.LineAddress);
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} else if (in_msg.Type == DMARequestType:WRITE) {
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trigger(Event:DMA_WRITE, in_msg.LineAddress);
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} else {
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error("Invalid message");
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}
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}
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}
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}
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in_port(requestQueue_in, RequestMsg, requestToDir) {
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if (requestQueue_in.isReady()) {
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peek(requestQueue_in, RequestMsg) {
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if (in_msg.Type == CoherenceRequestType:GETS) {
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trigger(Event:GETS, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:GETX) {
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trigger(Event:GETX, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:PUTX) {
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if (directory[in_msg.Address].Owner.isElement(in_msg.Requestor)) {
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trigger(Event:PUTX, in_msg.Address);
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} else {
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trigger(Event:PUTX_NotOwner, in_msg.Address);
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}
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} else {
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error("Invalid message");
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}
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}
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}
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}
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//added by SS
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// off-chip memory request/response is done
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in_port(memQueue_in, MemoryMsg, memBuffer) {
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if (memQueue_in.isReady()) {
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peek(memQueue_in, MemoryMsg) {
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if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
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trigger(Event:Memory_Data, in_msg.Address);
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} else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
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trigger(Event:Memory_Ack, in_msg.Address);
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} else {
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DEBUG_EXPR(in_msg.Type);
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error("Invalid message");
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}
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}
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}
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}
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// Actions
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action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
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peek(requestQueue_in, RequestMsg) {
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enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:WB_ACK;
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out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(l_sendWriteBackAck, "la", desc="Send writeback ack to requestor") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(forwardNetwork_out, RequestMsg, latency="1") {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:WB_ACK;
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out_msg.Requestor := in_msg.OriginalRequestorMachId;
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out_msg.Destination.add(in_msg.OriginalRequestorMachId);
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
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peek(requestQueue_in, RequestMsg) {
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enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:WB_NACK;
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out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(c_clearOwner, "c", desc="Clear the owner field") {
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directory[address].Owner.clear();
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}
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// action(d_sendData, "d", desc="Send data to requestor") {
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// peek(requestQueue_in, RequestMsg) {
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// enqueue(responseNetwork_out, ResponseMsg, latency="MEMORY_LATENCY") {
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// out_msg.Address := address;
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//
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// if (in_msg.Type == CoherenceRequestType:GETS && directory[address].Sharers.count() == 0) {
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// // out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE_CLEAN;
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// out_msg.Type := CoherenceResponseType:DATA;
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// } else {
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// out_msg.Type := CoherenceResponseType:DATA;
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// }
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//
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// out_msg.Sender := machineID;
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// out_msg.Destination.add(in_msg.Requestor);
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// out_msg.DataBlk := directory[in_msg.Address].DataBlk;
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// out_msg.MessageSize := MessageSizeType:Response_Data;
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// }
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// }
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// }
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action(d_sendData, "d", desc="Send data to requestor") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency="1") {
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.OriginalRequestorMachId);
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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// action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
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// peek(dmaRequestQueue_in, DMARequestMsg) {
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// enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") {
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// out_msg.PhysicalAddress := address;
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// out_msg.Type := DMAResponseType:DATA;
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// out_msg.DataBlk := directory[in_msg.PhysicalAddress].DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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// out_msg.Destination.add(map_Address_to_DMA(address));
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// out_msg.MessageSize := MessageSizeType:Response_Data;
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// }
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// }
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// }
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action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
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out_msg.PhysicalAddress := address;
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
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peek(requestQueue_in, RequestMsg) {
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enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
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out_msg.PhysicalAddress := address;
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
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enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
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out_msg.PhysicalAddress := address;
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:ACK;
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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action(d_deallocateDirectory, "\d", desc="Deallocate Directory Entry") {
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directory.invalidateBlock(address);
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}
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action(e_ownerIsRequestor, "e", desc="The owner is now the requestor") {
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peek(requestQueue_in, RequestMsg) {
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directory[address].Owner.clear();
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directory[address].Owner.add(in_msg.Requestor);
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}
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}
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action(f_forwardRequest, "f", desc="Forward request to owner") {
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peek(requestQueue_in, RequestMsg) {
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APPEND_TRANSITION_COMMENT("Own: ");
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APPEND_TRANSITION_COMMENT(directory[in_msg.Address].Owner);
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APPEND_TRANSITION_COMMENT("Req: ");
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APPEND_TRANSITION_COMMENT(in_msg.Requestor);
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enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
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out_msg.Address := address;
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out_msg.Type := in_msg.Type;
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out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination := directory[in_msg.Address].Owner;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:INV;
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out_msg.Requestor := machineID;
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out_msg.Destination := directory[in_msg.PhysicalAddress].Owner;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") {
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requestQueue_in.dequeue();
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}
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action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
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dmaRequestQueue_in.dequeue();
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}
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action(l_writeDataToMemory, "l", desc="Write PUTX data to memory") {
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peek(requestQueue_in, RequestMsg) {
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// assert(in_msg.Dirty);
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// assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
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directory[in_msg.Address].DataBlk := in_msg.DataBlk;
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DEBUG_EXPR(in_msg.Address);
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DEBUG_EXPR(in_msg.DataBlk);
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}
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}
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action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
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directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
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}
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action(v_allocateTBE, "v", desc="Allocate TBE") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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TBEs.allocate(address);
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TBEs[address].DataBlk := in_msg.DataBlk;
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TBEs[address].PhysicalAddress := in_msg.PhysicalAddress;
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TBEs[address].Len := in_msg.Len;
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}
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}
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action(v_allocateTBEFromRequestNet, "\v", desc="Allocate TBE") {
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peek(requestQueue_in, RequestMsg) {
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TBEs.allocate(address);
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TBEs[address].DataBlk := in_msg.DataBlk;
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}
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}
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action(w_deallocateTBE, "w", desc="Deallocate TBE") {
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TBEs.deallocate(address);
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}
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action(z_recycleRequestQueue, "z", desc="recycle request queue") {
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requestQueue_in.recycle();
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}
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action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
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peek(requestQueue_in, RequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency="1") {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_READ;
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out_msg.Sender := machineID;
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out_msg.OriginalRequestorMachId := in_msg.Requestor;
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out_msg.MessageSize := in_msg.MessageSize;
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out_msg.DataBlk := directory[in_msg.Address].DataBlk;
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DEBUG_EXPR(out_msg);
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}
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}
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}
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action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency="1") {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_READ;
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out_msg.Sender := machineID;
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//out_msg.OriginalRequestorMachId := machineID;
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out_msg.MessageSize := in_msg.MessageSize;
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out_msg.DataBlk := directory[address].DataBlk;
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DEBUG_EXPR(out_msg);
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}
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}
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}
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// action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
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// peek(dmaRequestQueue_in, DMARequestMsg) {
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// enqueue(memQueue_out, MemoryMsg, latency="1") {
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// out_msg.Address := address;
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// out_msg.Type := MemoryRequestType:MEMORY_WB;
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// out_msg.OriginalRequestorMachId := machineID;
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// out_msg.DataBlk := in_msg.DataBlk;
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// out_msg.MessageSize := in_msg.MessageSize;
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// DEBUG_EXPR(out_msg);
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// }
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// }
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// }
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action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency="1") {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_WB;
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//out_msg.OriginalRequestorMachId := machineID;
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//out_msg.DataBlk := in_msg.DataBlk;
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out_msg.DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.PhysicalAddress), in_msg.Len);
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out_msg.MessageSize := in_msg.MessageSize;
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//out_msg.Prefetch := in_msg.Prefetch;
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DEBUG_EXPR(out_msg);
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}
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}
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}
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action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip writeback request") {
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peek(requestQueue_in, RequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency="1") {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_WB;
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out_msg.OriginalRequestorMachId := in_msg.Requestor;
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//out_msg.DataBlk := in_msg.DataBlk;
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out_msg.DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
|
|
out_msg.MessageSize := in_msg.MessageSize;
|
|
//out_msg.Prefetch := in_msg.Prefetch;
|
|
|
|
DEBUG_EXPR(out_msg);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
action(l_queueMemoryWBRequest, "lq", desc="Write PUTX data to memory") {
|
|
peek(requestQueue_in, RequestMsg) {
|
|
enqueue(memQueue_out, MemoryMsg, latency="1") {
|
|
out_msg.Address := address;
|
|
out_msg.Type := MemoryRequestType:MEMORY_WB;
|
|
out_msg.OriginalRequestorMachId := in_msg.Requestor;
|
|
out_msg.DataBlk := in_msg.DataBlk;
|
|
out_msg.MessageSize := in_msg.MessageSize;
|
|
//out_msg.Prefetch := in_msg.Prefetch;
|
|
|
|
DEBUG_EXPR(out_msg);
|
|
}
|
|
}
|
|
}
|
|
|
|
action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
|
|
memQueue_in.dequeue();
|
|
}
|
|
|
|
action(w_writeDataToMemoryFromTBE, "\w", desc="Write date to directory memory from TBE") {
|
|
directory[address].DataBlk := TBEs[address].DataBlk;
|
|
}
|
|
|
|
// TRANSITIONS
|
|
|
|
transition({M_DRD, M_DWR}, GETX) {
|
|
z_recycleRequestQueue;
|
|
}
|
|
|
|
transition({IM, MI, ID, ID_W}, {GETX, GETS, DMA_READ, DMA_WRITE, PUTX, PUTX_NotOwner} ) {
|
|
z_recycleRequestQueue;
|
|
}
|
|
|
|
transition(I, GETX, IM) {
|
|
//d_sendData;
|
|
qf_queueMemoryFetchRequest;
|
|
e_ownerIsRequestor;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(IM, Memory_Data, M) {
|
|
d_sendData;
|
|
//e_ownerIsRequestor;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
|
|
transition(I, DMA_READ, ID) {
|
|
//dr_sendDMAData;
|
|
qf_queueMemoryFetchRequestDMA;
|
|
p_popIncomingDMARequestQueue;
|
|
}
|
|
|
|
transition(ID, Memory_Data, I) {
|
|
dr_sendDMAData;
|
|
//p_popIncomingDMARequestQueue;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
|
|
|
|
transition(I, DMA_WRITE, ID_W) {
|
|
v_allocateTBE;
|
|
qw_queueMemoryWBRequest_partial;
|
|
p_popIncomingDMARequestQueue;
|
|
}
|
|
|
|
transition(ID_W, Memory_Ack, I) {
|
|
dwt_writeDMADataFromTBE;
|
|
da_sendDMAAck;
|
|
w_deallocateTBE;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
transition(M, DMA_READ, M_DRD) {
|
|
inv_sendCacheInvalidate;
|
|
p_popIncomingDMARequestQueue;
|
|
}
|
|
|
|
transition(M_DRD, PUTX, I) {
|
|
drp_sendDMAData;
|
|
c_clearOwner;
|
|
a_sendWriteBackAck;
|
|
d_deallocateDirectory;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(M, DMA_WRITE, M_DWR) {
|
|
v_allocateTBE;
|
|
inv_sendCacheInvalidate;
|
|
p_popIncomingDMARequestQueue;
|
|
}
|
|
|
|
transition(M_DWR, PUTX, M_DWRI) {
|
|
qw_queueMemoryWBRequest_partialTBE;
|
|
c_clearOwner;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(M_DWRI, Memory_Ack, I) {
|
|
w_writeDataToMemoryFromTBE;
|
|
l_sendWriteBackAck;
|
|
da_sendDMAAck;
|
|
w_deallocateTBE;
|
|
d_deallocateDirectory;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
transition(M, GETX, M) {
|
|
f_forwardRequest;
|
|
e_ownerIsRequestor;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(M, PUTX, MI) {
|
|
c_clearOwner;
|
|
v_allocateTBEFromRequestNet;
|
|
l_queueMemoryWBRequest;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(MI, Memory_Ack, I) {
|
|
w_writeDataToMemoryFromTBE;
|
|
l_sendWriteBackAck;
|
|
w_deallocateTBE;
|
|
d_deallocateDirectory;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
transition(M, PUTX_NotOwner, M) {
|
|
b_sendWriteBackNack;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(I, PUTX_NotOwner, I) {
|
|
b_sendWriteBackNack;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
}
|