747 lines
83 KiB
Text
747 lines
83 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.081957 # Number of seconds simulated
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sim_ticks 81956970500 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 32873 # Simulator instruction rate (inst/s)
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host_tick_rate 51935468 # Simulator tick rate (ticks/s)
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host_mem_usage 384040 # Number of bytes of host memory used
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host_seconds 1578.05 # Real time elapsed on the host
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sim_insts 51876153 # Number of instructions simulated
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system.l2c.replacements 94702 # number of replacements
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system.l2c.tagsinuse 38059.464310 # Cycle average of tags in use
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system.l2c.total_refs 1031447 # Total number of references to valid blocks.
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system.l2c.sampled_refs 126964 # Sample count of references to valid blocks.
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system.l2c.avg_refs 8.123933 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::0 6535.540690 # Average occupied blocks per context
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system.l2c.occ_blocks::1 31523.923619 # Average occupied blocks per context
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system.l2c.occ_percent::0 0.099724 # Average percentage of cache occupancy
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system.l2c.occ_percent::1 0.481017 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::0 732124 # number of ReadReq hits
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system.l2c.ReadReq_hits::1 105939 # number of ReadReq hits
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system.l2c.ReadReq_hits::total 838063 # number of ReadReq hits
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system.l2c.Writeback_hits::0 432446 # number of Writeback hits
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system.l2c.Writeback_hits::total 432446 # number of Writeback hits
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system.l2c.UpgradeReq_hits::0 20 # number of UpgradeReq hits
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system.l2c.UpgradeReq_hits::total 20 # number of UpgradeReq hits
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system.l2c.ReadExReq_hits::0 60973 # number of ReadExReq hits
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system.l2c.ReadExReq_hits::total 60973 # number of ReadExReq hits
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system.l2c.demand_hits::0 793097 # number of demand (read+write) hits
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system.l2c.demand_hits::1 105939 # number of demand (read+write) hits
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system.l2c.demand_hits::total 899036 # number of demand (read+write) hits
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system.l2c.overall_hits::0 793097 # number of overall hits
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system.l2c.overall_hits::1 105939 # number of overall hits
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|
system.l2c.overall_hits::total 899036 # number of overall hits
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system.l2c.ReadReq_misses::0 20401 # number of ReadReq misses
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system.l2c.ReadReq_misses::1 101 # number of ReadReq misses
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system.l2c.ReadReq_misses::total 20502 # number of ReadReq misses
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system.l2c.UpgradeReq_misses::0 1673 # number of UpgradeReq misses
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|
system.l2c.UpgradeReq_misses::total 1673 # number of UpgradeReq misses
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system.l2c.ReadExReq_misses::0 107993 # number of ReadExReq misses
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system.l2c.ReadExReq_misses::total 107993 # number of ReadExReq misses
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system.l2c.demand_misses::0 128394 # number of demand (read+write) misses
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system.l2c.demand_misses::1 101 # number of demand (read+write) misses
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system.l2c.demand_misses::total 128495 # number of demand (read+write) misses
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system.l2c.overall_misses::0 128394 # number of overall misses
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system.l2c.overall_misses::1 101 # number of overall misses
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system.l2c.overall_misses::total 128495 # number of overall misses
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system.l2c.ReadReq_miss_latency 1071402500 # number of ReadReq miss cycles
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system.l2c.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles
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system.l2c.ReadExReq_miss_latency 5664440500 # number of ReadExReq miss cycles
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system.l2c.demand_miss_latency 6735843000 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency 6735843000 # number of overall miss cycles
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system.l2c.ReadReq_accesses::0 752525 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::1 106040 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::total 858565 # number of ReadReq accesses(hits+misses)
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system.l2c.Writeback_accesses::0 432446 # number of Writeback accesses(hits+misses)
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|
system.l2c.Writeback_accesses::total 432446 # number of Writeback accesses(hits+misses)
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|
system.l2c.UpgradeReq_accesses::0 1693 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::total 1693 # number of UpgradeReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::0 168966 # number of ReadExReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::total 168966 # number of ReadExReq accesses(hits+misses)
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system.l2c.demand_accesses::0 921491 # number of demand (read+write) accesses
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system.l2c.demand_accesses::1 106040 # number of demand (read+write) accesses
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system.l2c.demand_accesses::total 1027531 # number of demand (read+write) accesses
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system.l2c.overall_accesses::0 921491 # number of overall (read+write) accesses
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system.l2c.overall_accesses::1 106040 # number of overall (read+write) accesses
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system.l2c.overall_accesses::total 1027531 # number of overall (read+write) accesses
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system.l2c.ReadReq_miss_rate::0 0.027110 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::1 0.000952 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::total 0.028063 # miss rate for ReadReq accesses
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system.l2c.UpgradeReq_miss_rate::0 0.988187 # miss rate for UpgradeReq accesses
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|
system.l2c.ReadExReq_miss_rate::0 0.639140 # miss rate for ReadExReq accesses
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|
system.l2c.demand_miss_rate::0 0.139333 # miss rate for demand accesses
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system.l2c.demand_miss_rate::1 0.000952 # miss rate for demand accesses
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system.l2c.demand_miss_rate::total 0.140285 # miss rate for demand accesses
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system.l2c.overall_miss_rate::0 0.139333 # miss rate for overall accesses
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system.l2c.overall_miss_rate::1 0.000952 # miss rate for overall accesses
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system.l2c.overall_miss_rate::total 0.140285 # miss rate for overall accesses
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system.l2c.ReadReq_avg_miss_latency::0 52517.156022 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::1 10607945.544554 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::total 10660462.700576 # average ReadReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::0 435.445308 # average UpgradeReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::0 52451.922810 # average ReadExReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
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|
system.l2c.demand_avg_miss_latency::0 52462.287957 # average overall miss latency
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system.l2c.demand_avg_miss_latency::1 66691514.851485 # average overall miss latency
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system.l2c.demand_avg_miss_latency::total 66743977.139443 # average overall miss latency
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system.l2c.overall_avg_miss_latency::0 52462.287957 # average overall miss latency
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system.l2c.overall_avg_miss_latency::1 66691514.851485 # average overall miss latency
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system.l2c.overall_avg_miss_latency::total 66743977.139443 # average overall miss latency
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.l2c.fast_writes 0 # number of fast writes performed
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system.l2c.cache_copies 0 # number of cache copies performed
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system.l2c.writebacks 87773 # number of writebacks
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system.l2c.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits
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system.l2c.demand_mshr_hits 47 # number of demand (read+write) MSHR hits
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system.l2c.overall_mshr_hits 47 # number of overall MSHR hits
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system.l2c.ReadReq_mshr_misses 20455 # number of ReadReq MSHR misses
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system.l2c.UpgradeReq_mshr_misses 1673 # number of UpgradeReq MSHR misses
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system.l2c.ReadExReq_mshr_misses 107993 # number of ReadExReq MSHR misses
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|
system.l2c.demand_mshr_misses 128448 # number of demand (read+write) MSHR misses
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|
system.l2c.overall_mshr_misses 128448 # number of overall MSHR misses
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system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.l2c.ReadReq_mshr_miss_latency 819077500 # number of ReadReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency 66920000 # number of UpgradeReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency 4321060500 # number of ReadExReq MSHR miss cycles
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system.l2c.demand_mshr_miss_latency 5140138000 # number of demand (read+write) MSHR miss cycles
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system.l2c.overall_mshr_miss_latency 5140138000 # number of overall MSHR miss cycles
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system.l2c.ReadReq_mshr_uncacheable_latency 28946041000 # number of ReadReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency 748279439 # number of WriteReq MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency 29694320439 # number of overall MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_miss_rate::0 0.027182 # mshr miss rate for ReadReq accesses
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system.l2c.ReadReq_mshr_miss_rate::1 0.192899 # mshr miss rate for ReadReq accesses
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system.l2c.ReadReq_mshr_miss_rate::total 0.220081 # mshr miss rate for ReadReq accesses
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|
system.l2c.UpgradeReq_mshr_miss_rate::0 0.988187 # mshr miss rate for UpgradeReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::0 0.639140 # mshr miss rate for ReadExReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
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|
system.l2c.demand_mshr_miss_rate::0 0.139391 # mshr miss rate for demand accesses
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|
system.l2c.demand_mshr_miss_rate::1 1.211316 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::total 1.350708 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::0 0.139391 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::1 1.211316 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::total 1.350708 # mshr miss rate for overall accesses
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system.l2c.ReadReq_avg_mshr_miss_latency 40042.899047 # average ReadReq mshr miss latency
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system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.l2c.ReadExReq_avg_mshr_miss_latency 40012.412842 # average ReadExReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency 40017.267688 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency 40017.267688 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
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system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 27773403 # DTB read hits
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system.cpu.dtb.read_misses 62999 # DTB read misses
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system.cpu.dtb.write_hits 7478070 # DTB write hits
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system.cpu.dtb.write_misses 11819 # DTB write misses
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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|
system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
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|
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
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|
system.cpu.dtb.flush_entries 2909 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 3199 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 1081 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 1182 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 27836402 # DTB read accesses
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system.cpu.dtb.write_accesses 7489889 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 35251473 # DTB hits
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system.cpu.dtb.misses 74818 # DTB misses
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system.cpu.dtb.accesses 35326291 # DTB accesses
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system.cpu.itb.inst_hits 6378307 # ITB inst hits
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system.cpu.itb.inst_misses 7071 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
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|
system.cpu.itb.flush_entries 1627 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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|
system.cpu.itb.perms_faults 5145 # Number of TLB faults due to permissions restrictions
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|
system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 6385378 # ITB inst accesses
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system.cpu.itb.hits 6378307 # DTB hits
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system.cpu.itb.misses 7071 # DTB misses
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system.cpu.itb.accesses 6385378 # DTB accesses
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system.cpu.numCycles 163913942 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 12907993 # Number of BP lookups
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|
system.cpu.BPredUnit.condPredicted 10988942 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 671137 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 11440578 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 8975415 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 783446 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 155600 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 6371114 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 62781923 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 12907993 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 9758861 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 15757873 # Number of cycles fetch has run and was not squashing or blocked
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|
system.cpu.fetch.SquashCycles 1054135 # Number of cycles fetch has spent squashing
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|
system.cpu.fetch.TlbCycles 7071 # Number of cycles fetch has spent waiting for tlb
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|
system.cpu.fetch.MiscStallCycles 17008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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|
system.cpu.fetch.CacheLines 6372584 # Number of cache lines fetched
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|
system.cpu.fetch.IcacheSquashes 264714 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 3927 # Number of outstanding ITLB misses that were squashed
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|
system.cpu.fetch.rateDist::samples 94752246 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.818183 # Number of instructions fetched each cycle (Total)
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|
system.cpu.fetch.rateDist::stdev 2.071967 # Number of instructions fetched each cycle (Total)
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|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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|
system.cpu.fetch.rateDist::0 79011674 83.39% 83.39% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1184236 1.25% 84.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1729223 1.82% 86.46% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 1152880 1.22% 87.68% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 4802064 5.07% 92.75% # Number of instructions fetched each cycle (Total)
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|
system.cpu.fetch.rateDist::5 820808 0.87% 93.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 792852 0.84% 94.45% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 714149 0.75% 95.20% # Number of instructions fetched each cycle (Total)
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|
system.cpu.fetch.rateDist::8 4544360 4.80% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 94752246 # Number of instructions fetched each cycle (Total)
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|
system.cpu.fetch.branchRate 0.078749 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.383018 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 23351217 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 53571370 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 14396920 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 1001314 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 2431425 # Number of cycles decode is squashing
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|
system.cpu.decode.BranchResolved 1204609 # Number of times decode resolved a branch
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|
system.cpu.decode.BranchMispred 71112 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 75302047 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 237029 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 2431425 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 24915043 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 33439496 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 16240153 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 12813964 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 4912165 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 72500713 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 458049 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 112730 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 2517697 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 125 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 74405789 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 315201303 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 315135556 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 65747 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 51886765 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 22519023 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 806998 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 658881 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 13649364 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 12530731 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 8670127 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 2363 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 8454 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 64971047 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 4028155 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 80215912 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 157537 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 16406339 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 29306942 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1065284 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 94752246 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.846586 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.419375 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 59642752 62.95% 62.95% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 15646635 16.51% 79.46% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 6436241 6.79% 86.25% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 4342320 4.58% 90.83% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 6236918 6.58% 97.42% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 1389324 1.47% 98.88% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 710831 0.75% 99.63% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 267243 0.28% 99.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 79982 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 94752246 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 27052 0.56% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 1 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 4512476 93.02% 93.58% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 311301 6.42% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 2393223 2.98% 2.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 41066468 51.19% 54.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 70508 0.09% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 1 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 7 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 885 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 28697043 35.77% 90.04% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 7987756 9.96% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 80215912 # Type of FU issued
|
|
system.cpu.iq.rate 0.489378 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 4850830 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.060472 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 260250560 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 85669706 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 61171405 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 16469 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 9406 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 6426 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 82664896 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 8623 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 366873 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 3351745 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 17637 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 321029 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1592843 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 17031974 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 9614 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 2431425 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 21357875 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 254886 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 69165110 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 377919 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 12530731 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 8670127 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 3998128 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 20657 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 45624 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 321029 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 537696 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 192380 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 730076 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 79002177 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 28266423 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1213735 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 165908 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 36059018 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 10339734 # Number of branches executed
|
|
system.cpu.iew.exec_stores 7792595 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.481974 # Inst execution rate
|
|
system.cpu.iew.wb_sent 78480189 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 61177831 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 31697588 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 56147470 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.373231 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.564542 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitCommittedInsts 51999383 # The number of committed instructions
|
|
system.cpu.commit.commitSquashedInsts 14908448 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 2962871 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 647540 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 92320849 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.563246 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.403184 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 71715015 77.68% 77.68% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 9932500 10.76% 88.44% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 3015414 3.27% 91.71% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 1450347 1.57% 93.28% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 3545032 3.84% 97.12% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 778946 0.84% 97.96% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 574470 0.62% 98.58% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 309664 0.34% 98.92% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 999461 1.08% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 92320849 # Number of insts commited each cycle
|
|
system.cpu.commit.count 51999383 # Number of instructions committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 16256270 # Number of memory references committed
|
|
system.cpu.commit.loads 9178986 # Number of loads committed
|
|
system.cpu.commit.membars 3 # Number of memory barriers committed
|
|
system.cpu.commit.branches 8429045 # Number of branches committed
|
|
system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 42422970 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 530172 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 999461 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 157288126 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 136297259 # The number of ROB writes
|
|
system.cpu.timesIdled 1087126 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 69161696 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 51876153 # Number of Instructions Simulated
|
|
system.cpu.committedInsts_total 51876153 # Number of Instructions Simulated
|
|
system.cpu.cpi 3.159717 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 3.159717 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.316484 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.316484 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 348377421 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 63134850 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 5557 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 1914 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 83038352 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 512623 # number of misc regfile writes
|
|
system.cpu.icache.replacements 500212 # number of replacements
|
|
system.cpu.icache.tagsinuse 496.830420 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 5827483 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 500724 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 11.638114 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 6079257000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::0 496.830420 # Average occupied blocks per context
|
|
system.cpu.icache.occ_percent::0 0.970372 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::0 5827483 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 5827483 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::0 5827483 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 5827483 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::0 5827483 # number of overall hits
|
|
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 5827483 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::0 545006 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 545006 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::0 545006 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 545006 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::0 545006 # number of overall misses
|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 545006 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency 8053875993 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency 8053875993 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency 8053875993 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::0 6372489 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 6372489 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::0 6372489 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 6372489 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::0 6372489 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 6372489 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.085525 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::0 0.085525 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::0 0.085525 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::0 14777.591427 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::0 14777.591427 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::0 14777.591427 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 923494 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 110 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 8395.400000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks 41542 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits 44276 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits 44276 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits 44276 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses 500730 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses 500730 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses 500730 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 6024482994 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency 6024482994 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency 6024482994 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency 5116500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 5116500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.078577 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.078577 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.078577 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12031.400144 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 12031.400144 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 12031.400144 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 422669 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.748488 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 13739336 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 423181 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 32.466807 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 48245000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::0 511.748488 # Average occupied blocks per context
|
|
system.cpu.dcache.occ_percent::0 0.999509 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::0 8909058 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 8909058 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::0 4618812 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4618812 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::0 104652 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 104652 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::0 105045 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 105045 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::0 13527870 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 13527870 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::0 13527870 # number of overall hits
|
|
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 13527870 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::0 535094 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 535094 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::0 2043981 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2043981 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::0 6519 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 6519 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::0 2579075 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2579075 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::0 2579075 # number of overall misses
|
|
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2579075 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency 7852770500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency 81637630250 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 97499500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency 89490400750 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency 89490400750 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::0 9444152 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9444152 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::0 6662793 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6662793 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::0 111171 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 111171 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::0 105045 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 105045 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::0 16106945 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 16106945 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::0 16106945 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 16106945 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::0 0.056659 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::0 0.306775 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058639 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::0 0.160122 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::0 0.160122 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::0 14675.497202 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::0 39940.503483 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14956.204939 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::0 34698.642246 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::0 34698.642246 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 8797482 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 743000 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1156 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7610.278547 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 26535.714286 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks 390904 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits 286385 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits 1873352 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 983 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits 2159737 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits 2159737 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses 248709 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses 170629 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses 5536 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses 419338 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses 419338 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 3317944000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 6570142982 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65837500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency 9888086982 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency 9888086982 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38198704500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 944337693 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 39143042193 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026335 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025609 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.049797 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::0 0.026035 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::0 0.026035 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13340.667205 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38505.429804 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11892.611994 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 23580.231179 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 23580.231179 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
system.iocache.overall_misses::1 0 # number of overall misses
|
|
system.iocache.overall_misses::total 0 # number of overall misses
|
|
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks 0 # number of writebacks
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
|
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
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