2163 lines
255 KiB
Text
2163 lines
255 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 51.811486 # Number of seconds simulated
|
|
sim_ticks 51811486345500 # Number of ticks simulated
|
|
final_tick 51811486345500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 353733 # Simulator instruction rate (inst/s)
|
|
host_op_rate 415699 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 22175355428 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 671232 # Number of bytes of host memory used
|
|
host_seconds 2336.44 # Real time elapsed on the host
|
|
sim_insts 826478524 # Number of instructions simulated
|
|
sim_ops 971257944 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::cpu0.dtb.walker 67136 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.itb.walker 69696 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.inst 2388444 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.data 32434992 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.dtb.walker 59968 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.itb.walker 68096 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.inst 2361560 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.data 31996376 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::realview.ide 390912 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 69837180 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu0.inst 2388444 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu1.inst 2361560 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 4750004 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 60588032 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu0.data 15876 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu1.data 4704 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 60608612 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu0.dtb.walker 1049 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.itb.walker 1089 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.inst 57981 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.data 506800 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.dtb.walker 937 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.itb.walker 1064 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.inst 56645 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.data 499953 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::realview.ide 6108 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 1131626 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 946688 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu0.data 1985 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu1.data 588 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 949261 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu0.dtb.walker 1296 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.itb.walker 1345 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.inst 46099 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.data 626019 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.dtb.walker 1157 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.itb.walker 1314 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.inst 45580 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.data 617554 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::realview.ide 7545 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 1347909 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu0.inst 46099 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu1.inst 45580 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 91679 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 1169394 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu0.data 306 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu1.data 91 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 1169791 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 1169394 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.dtb.walker 1296 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.itb.walker 1345 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.inst 46099 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.data 626326 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.dtb.walker 1157 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.itb.walker 1314 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.inst 45580 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.data 617645 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::realview.ide 7545 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 2517700 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 1131626 # Number of read requests accepted
|
|
system.physmem.writeReqs 949261 # Number of write requests accepted
|
|
system.physmem.readBursts 1131626 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 949261 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 72380992 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 43072 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 60608832 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 69837180 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 60608612 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 673 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 139894 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 75334 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 78749 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 69239 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 66964 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 64795 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 72549 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 64584 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 63831 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 65287 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 109012 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 67637 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 66460 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 64061 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 68282 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 66426 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 67743 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 61340 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 64755 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 59195 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 59472 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 56881 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 61983 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 56876 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 57630 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 57576 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 59174 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 59811 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 59738 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 56644 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 59454 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 57794 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 58690 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 24 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 51811483663500 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 43101 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 13 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 2 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 1088510 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 1 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 946688 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 1104614 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 20819 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 387 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 319 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 461 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 554 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 482 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 1115 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 633 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 273 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 323 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 163 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 159 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 117 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 1575 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 1529 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 1505 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 1483 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 1461 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 1452 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 1432 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1416 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1399 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1383 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1360 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1350 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1337 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1328 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1319 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 13766 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 16565 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 52866 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 53787 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 55478 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 54927 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 55914 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 55859 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 57161 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 56694 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 56942 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 61202 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 56246 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 54836 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 55477 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 53687 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 52944 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 52255 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 1021 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 720 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 609 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 524 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 524 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 457 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 454 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 393 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 296 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 355 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 249 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 303 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 227 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 221 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 274 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 242 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 260 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 245 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 192 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 213 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 149 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 158 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 145 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 107 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 112 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 96 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 106 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 68 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 441668 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 301.107402 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 173.680008 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 331.161317 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 174892 39.60% 39.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 107627 24.37% 63.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 38708 8.76% 72.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 22457 5.08% 77.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 15602 3.53% 81.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 11601 2.63% 83.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 10181 2.31% 86.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 8589 1.94% 88.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 52011 11.78% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 441668 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 52978 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 21.347484 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 294.800530 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-2047 52971 99.99% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::2048-4095 3 0.01% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::6144-8191 2 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 52978 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 52978 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 17.875590 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 17.137628 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 7.848761 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::0-3 99 0.19% 0.19% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::4-7 70 0.13% 0.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::8-11 74 0.14% 0.46% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::12-15 116 0.22% 0.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 49442 93.33% 94.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 558 1.05% 95.06% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 385 0.73% 95.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 568 1.07% 96.86% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 120 0.23% 97.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 330 0.62% 97.70% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 204 0.39% 98.09% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 24 0.05% 98.14% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 95 0.18% 98.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 130 0.25% 98.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 29 0.05% 98.61% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 30 0.06% 98.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 454 0.86% 99.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 21 0.04% 99.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 29 0.05% 99.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 141 0.27% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 7 0.01% 99.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 29 0.05% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 8 0.02% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 52978 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 13921987827 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 35127356577 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 5654765000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 12309.96 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 31059.96 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 1.40 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 1.35 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 7.63 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 914287 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 722010 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 80.84 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 76.24 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 24898749.27 # Average gap between requests
|
|
system.physmem.pageHitRate 78.75 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 1737469440 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 948024000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 4337112000 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 3098295360 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 3384074191680 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 1302776002665 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 29944103839500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 34641074934645 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 668.598406 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 49814086335255 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 1730099280000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 267300073745 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 1601540640 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 873856500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 4484282400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 3038348880 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 3384074191680 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 1289689159770 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 29955583526250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 34639344906120 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 668.565015 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 49833230042430 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1730099280000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 248153702570 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.walker.walks 116564 # Table walker walks requested
|
|
system.cpu0.dtb.walker.walksLong 116564 # Table walker walks initiated with long descriptors
|
|
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17888 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84633 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting
|
|
system.cpu0.dtb.walker.walkWaitTime::samples 116551 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::mean 0.308878 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::stdev 85.298018 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::0-2047 116549 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::total 116551 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::samples 102534 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::mean 24964.241130 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::gmean 21649.871180 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::stdev 15929.030690 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::0-65535 101954 99.43% 99.43% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 9 0.01% 99.44% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 497 0.48% 99.93% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 10 0.01% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 33 0.03% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 15 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::total 102534 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walksPending::samples -4616128984 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::mean 1.375220 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::0 1732065704 -37.52% -37.52% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::1 -6348194688 137.52% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::total -4616128984 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walkPageSizes::4K 84634 82.55% 82.55% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::2M 17888 17.45% 100.00% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::total 102522 # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 116564 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 116564 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 102522 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 102522 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin::total 219086 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 77762076 # DTB read hits
|
|
system.cpu0.dtb.read_misses 89597 # DTB read misses
|
|
system.cpu0.dtb.write_hits 70744341 # DTB write hits
|
|
system.cpu0.dtb.write_misses 26967 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 51819 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 18784 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 68559 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 3939 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 9342 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 77851673 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 70771308 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 148506417 # DTB hits
|
|
system.cpu0.dtb.misses 116564 # DTB misses
|
|
system.cpu0.dtb.accesses 148622981 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.walker.walks 74612 # Table walker walks requested
|
|
system.cpu0.itb.walker.walksLong 74612 # Table walker walks initiated with long descriptors
|
|
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4209 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 65365 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.itb.walker.walkWaitTime::samples 74612 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::0 74612 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::total 74612 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::samples 69574 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::mean 28527.819300 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::gmean 25311.121928 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::stdev 18888.333067 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::0-65535 68887 99.01% 99.01% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::65536-131071 3 0.00% 99.02% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::131072-196607 590 0.85% 99.86% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::196608-262143 20 0.03% 99.89% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::262144-327679 39 0.06% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::393216-458751 13 0.02% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::total 69574 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walksPending::samples 1705681704 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::0 1705681704 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::total 1705681704 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walkPageSizes::4K 65365 93.95% 93.95% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::2M 4209 6.05% 100.00% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::total 69574 # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 74612 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 74612 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 69574 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 69574 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin::total 144186 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.inst_hits 414226266 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 74612 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 51819 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 18784 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 50668 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 414300878 # ITB inst accesses
|
|
system.cpu0.itb.hits 414226266 # DTB hits
|
|
system.cpu0.itb.misses 74612 # DTB misses
|
|
system.cpu0.itb.accesses 414300878 # DTB accesses
|
|
system.cpu0.numCycles 51812404725 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 15960 # number of quiesce instructions executed
|
|
system.cpu0.committedInsts 413973920 # Number of instructions committed
|
|
system.cpu0.committedOps 486522682 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 447282441 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 436837 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 24924968 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 62713258 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 447282441 # number of integer instructions
|
|
system.cpu0.num_fp_insts 436837 # number of float instructions
|
|
system.cpu0.num_int_register_reads 647714944 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 354553253 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 705988 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 367364 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 107220558 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 106909360 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 148497129 # number of memory refs
|
|
system.cpu0.num_load_insts 77758052 # Number of load instructions
|
|
system.cpu0.num_store_insts 70739077 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 50264604442.745827 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 1547800282.254174 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.029873 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.970127 # Percentage of idle cycles
|
|
system.cpu0.Branches 92346942 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 337152189 69.26% 69.26% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 1046864 0.22% 69.47% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 47543 0.01% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 20 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 53325 0.01% 69.50% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 77758052 15.97% 85.47% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 70739077 14.53% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 486797091 # Class of executed instruction
|
|
system.cpu0.dcache.tags.replacements 9220536 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.942797 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 287472122 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 9221048 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 31.175645 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 5829979500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 266.571154 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 245.371643 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.520647 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.479241 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 1196444585 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 1196444585 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 72800073 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 72976033 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 145776106 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 67163987 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 66958173 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 134122160 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185807 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 184713 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 370520 # number of SoftPFReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162919 # number of WriteLineReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 167025 # number of WriteLineReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::total 329944 # number of WriteLineReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1640826 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1634541 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 3275367 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1783142 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1773309 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 3556451 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 139964060 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 139934206 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 279898266 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 140149867 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 140118919 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 280268786 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 2404547 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 2404611 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 4809158 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 998419 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 959819 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1958238 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 571068 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 532615 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 1103683 # number of SoftPFReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 611544 # number of WriteLineReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 610003 # number of WriteLineReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::total 1221547 # number of WriteLineReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 143187 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 139519 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 282706 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 3402966 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 3364430 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 6767396 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 3974034 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 3897045 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 7871079 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41475189000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 40798417000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 82273606000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33407894500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 32524052000 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 65931946500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 36223199500 # number of WriteLineReq miss cycles
|
|
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 36925470000 # number of WriteLineReq miss cycles
|
|
system.cpu0.dcache.WriteLineReq_miss_latency::total 73148669500 # number of WriteLineReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2177820000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2134271000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 4312091000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 82000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 74883083500 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 73322469000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 148205552500 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 74883083500 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 73322469000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 148205552500 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 75204620 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 75380644 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 150585264 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 68162406 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 67917992 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 136080398 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 756875 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 717328 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 1474203 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 774463 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 777028 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::total 1551491 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1784013 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 1774060 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 3558073 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1783142 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1773310 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 3556452 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 143367026 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 143298636 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 286665662 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 144123901 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 144015964 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 288139865 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031973 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031900 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.031936 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014648 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014132 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.014390 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.754508 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.742499 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.748664 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.789636 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.785046 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.787337 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080261 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078644 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079455 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.023736 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023478 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.023607 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027574 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027060 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.027317 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17248.649746 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16966.743062 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17107.694528 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 33460.796019 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 33885.609683 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 33669.015973 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59232.368399 # average WriteLineReq miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 60533.259672 # average WriteLineReq miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59881.993489 # average WriteLineReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15209.620985 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15297.350182 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15252.916457 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22005.239988 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21793.429793 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 21899.937953 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18843.090799 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18814.888974 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 18829.127811 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 7220092 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 7220092 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 12855 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 9702 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 22557 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 11438 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 9844 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 21282 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 33704 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 33408 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 67112 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 24293 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 19546 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 43839 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 24293 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 19546 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 43839 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2391692 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2394909 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 4786601 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 986981 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 949975 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 1936956 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 570124 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 531812 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 1101936 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 611544 # number of WriteLineReq MSHR misses
|
|
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 610003 # number of WriteLineReq MSHR misses
|
|
system.cpu0.dcache.WriteLineReq_mshr_misses::total 1221547 # number of WriteLineReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 109483 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 106111 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 215594 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 3378673 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 3344884 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 6723557 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 3948797 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 3876696 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 7825493 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16577 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17124 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33701 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16927 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 16781 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33504 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 33905 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67409 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38337908500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 37823855000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 76161763500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31904413500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 31123658000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 63028071500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10925929500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9736959500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20662889000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 35611655500 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 36315467000 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 71927122500 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1499957000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1452847000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2952804000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 81000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 70242322000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 68947513000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 139189835000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81168251500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 78684472500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 159852724000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2837606500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2994256500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5831863000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2838720500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2985129500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5823850000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5676327000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5979386000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11655713000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031802 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031771 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031787 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014480 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013987 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014234 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753260 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741379 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.747479 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.789636 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.785046 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787337 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061369 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059813 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060593 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023567 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023342 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023454 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027399 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026919 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.027159 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16029.617735 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15793.441421 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15911.450213 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32325.256008 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32762.607437 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32539.753872 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19164.128330 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18309.025558 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18751.442008 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58232.368399 # average WriteLineReq mshr miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59533.259672 # average WriteLineReq mshr miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58881.993489 # average WriteLineReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13700.364440 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13691.766169 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13696.132545 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20789.914265 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20612.826334 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20701.815274 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20555.184655 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20296.786877 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20427.176154 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171177.324003 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174857.305536 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173047.179609 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167703.698234 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177887.462011 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172773.525573 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 169422.367479 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176357.056481 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172910.338382 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 13375087 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.782407 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 813613327 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 13375599 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 60.828179 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 61699422500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 237.356539 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 274.425868 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.463587 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.535988 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 840364535 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 840364535 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 407513323 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 406100004 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 813613327 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 407513323 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 406100004 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 813613327 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 407513323 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 406100004 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 813613327 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 6712943 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 6662661 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 13375604 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 6712943 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 6662661 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 13375604 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 6712943 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 6662661 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 13375604 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 91656187500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 90957016000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 182613203500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 91656187500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 90957016000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 182613203500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 91656187500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 90957016000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 182613203500 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 414226266 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 412762665 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 826988931 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 414226266 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 412762665 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 826988931 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 414226266 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 412762665 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 826988931 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016206 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016142 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.016174 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016206 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016142 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.016174 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016206 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016142 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.016174 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13653.651982 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13651.755057 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13652.707085 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13653.651982 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13651.755057 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13652.707085 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13653.651982 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13651.755057 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13652.707085 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6712943 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6662661 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 13375604 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 6712943 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 6662661 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 13375604 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 6712943 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 6662661 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 13375604 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 22063 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 21062 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 22063 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 21062 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84943244500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 84294355000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 169237599500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 84943244500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 84294355000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 169237599500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 84943244500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 84294355000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 169237599500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780495500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2656027000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5436522500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2780495500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 2656027000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 5436522500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016206 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016142 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016174 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016206 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016142 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.016174 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016206 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016142 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.016174 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12653.651982 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12651.755057 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12652.707085 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12653.651982 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12651.755057 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12652.707085 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12653.651982 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12651.755057 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12652.707085 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126025.268549 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126105.165701 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126064.289855 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126025.268549 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126105.165701 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126064.289855 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.walker.walks 117457 # Table walker walks requested
|
|
system.cpu1.dtb.walker.walksLong 117457 # Table walker walks initiated with long descriptors
|
|
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17877 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85465 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.dtb.walker.walksSquashedBefore 15 # Table walks squashed before starting
|
|
system.cpu1.dtb.walker.walkWaitTime::samples 117442 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::mean 0.102178 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::stdev 35.016241 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::0-1023 117441 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::total 117442 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::samples 103357 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::mean 25041.496947 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::gmean 21746.242782 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::stdev 15395.142756 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::0-65535 102794 99.46% 99.46% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.46% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 506 0.49% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 8 0.01% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 24 0.02% 99.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 16 0.02% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::total 103357 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walksPending::samples 3996353148 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::mean 0.606452 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::stdev 0.488536 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::0 1572755204 39.35% 39.35% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::1 2423597944 60.65% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::total 3996353148 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walkPageSizes::4K 85465 82.70% 82.70% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::2M 17877 17.30% 100.00% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::total 103342 # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 117457 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 117457 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103342 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103342 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin::total 220799 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 77889145 # DTB read hits
|
|
system.cpu1.dtb.read_misses 90593 # DTB read misses
|
|
system.cpu1.dtb.write_hits 70493756 # DTB write hits
|
|
system.cpu1.dtb.write_misses 26864 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 51813 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 18879 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 486 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 67533 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 3800 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 9179 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 77979738 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 70520620 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 148382901 # DTB hits
|
|
system.cpu1.dtb.misses 117457 # DTB misses
|
|
system.cpu1.dtb.accesses 148500358 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.walker.walks 75165 # Table walker walks requested
|
|
system.cpu1.itb.walker.walksLong 75165 # Table walker walks initiated with long descriptors
|
|
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4147 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 65764 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.itb.walker.walkWaitTime::samples 75165 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::0 75165 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::total 75165 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::samples 69911 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::mean 28585.308464 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::gmean 25361.717379 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::stdev 18567.806598 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::0-65535 69206 98.99% 98.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::65536-131071 3 0.00% 99.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::131072-196607 615 0.88% 99.88% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::196608-262143 20 0.03% 99.90% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::262144-327679 34 0.05% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.01% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::393216-458751 19 0.03% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::total 69911 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walksPending::samples 1449365704 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::0 1449365704 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::total 1449365704 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walkPageSizes::4K 65764 94.07% 94.07% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::2M 4147 5.93% 100.00% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::total 69911 # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 75165 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 75165 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 69911 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 69911 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin::total 145076 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.inst_hits 412762665 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 75165 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 51813 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 18879 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 486 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 50171 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 412837830 # ITB inst accesses
|
|
system.cpu1.itb.hits 412762665 # DTB hits
|
|
system.cpu1.itb.misses 75165 # DTB misses
|
|
system.cpu1.itb.accesses 412837830 # DTB accesses
|
|
system.cpu1.numCycles 51810567966 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu1.committedInsts 412504604 # Number of instructions committed
|
|
system.cpu1.committedOps 484735262 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 445679810 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 461935 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 24743870 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 62553122 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 445679810 # number of integer instructions
|
|
system.cpu1.num_fp_insts 461935 # number of float instructions
|
|
system.cpu1.num_int_register_reads 643867148 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 353090786 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 745900 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 389388 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 106633710 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 106335348 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 148371142 # number of memory refs
|
|
system.cpu1.num_load_insts 77883866 # Number of load instructions
|
|
system.cpu1.num_store_insts 70487276 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 50277800640.138901 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 1532767325.861101 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.029584 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.970416 # Percentage of idle cycles
|
|
system.cpu1.Branches 92048959 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 335465896 69.17% 69.17% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 1068730 0.22% 69.39% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 49540 0.01% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 1 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 59074 0.01% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 77883866 16.06% 85.47% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 70487276 14.53% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 485014384 # Class of executed instruction
|
|
system.iobus.trans_dist::ReadReq 40322 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 40322 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 353786 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 7492360 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 565848755 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 147762000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 115483 # number of replacements
|
|
system.iocache.tags.tagsinuse 10.447157 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 13183753622000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ethernet 3.511463 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_blocks::realview.ide 6.935694 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.652947 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 1039866 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 1039866 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 8877 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
|
system.iocache.overall_misses::realview.ide 8837 # number of overall misses
|
|
system.iocache.overall_misses::total 8877 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::realview.ide 1638182519 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 1643251519 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::realview.ide 13826239236 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 13826239236 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 1638182519 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 1643602519 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 1638182519 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 1643602519 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 185377.675569 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 185175.965630 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129624.233443 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 129624.233443 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 185377.675569 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 185152.925425 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 185377.675569 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 185152.925425 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 32900 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 3381 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 9.730849 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
|
system.iocache.writebacks::total 106631 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1196332519 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 1199551519 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8493039236 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 8493039236 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 1196332519 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 1199752519 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 1196332519 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 1199752519 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135377.675569 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 135175.965630 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79624.233443 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79624.233443 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 135377.675569 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 135152.925425 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 135377.675569 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 135152.925425 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 991160 # number of replacements
|
|
system.l2c.tags.tagsinuse 65239.765860 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 41642303 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 1053414 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 39.530805 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 56092424500 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 37750.441132 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 111.130764 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 159.764623 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 4448.845209 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 10178.786628 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 88.140538 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.itb.walker 147.411941 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 4204.768278 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 8150.476748 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.576026 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001696 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.002438 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.067884 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.155316 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001345 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.itb.walker 0.002249 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.064160 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.124366 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.995480 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 303 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 61951 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 303 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 2426 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 5561 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 53526 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.004623 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.945297 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 371969368 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 371969368 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 206753 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 156932 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 209510 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 158543 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 731738 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 7220092 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 7220092 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 4469 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 4434 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 8903 # number of UpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 808716 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 774561 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 1583277 # number of ReadExReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 6676988 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 6627078 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 13304066 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 2957591 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 2929428 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 5887019 # number of ReadSharedReq hits
|
|
system.l2c.InvalidateReq_hits::cpu0.data 375245 # number of InvalidateReq hits
|
|
system.l2c.InvalidateReq_hits::cpu1.data 367579 # number of InvalidateReq hits
|
|
system.l2c.InvalidateReq_hits::total 742824 # number of InvalidateReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 206753 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 156932 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 6676988 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 3766307 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 209510 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 158543 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 6627078 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 3703989 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 21506100 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 206753 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 156932 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 6676988 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 3766307 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 209510 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 158543 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 6627078 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 3703989 # number of overall hits
|
|
system.l2c.overall_hits::total 21506100 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 1049 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 1089 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 937 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.itb.walker 1064 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 4139 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 16379 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 16291 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 32670 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 157417 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 154689 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 312106 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 35955 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 35583 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 71538 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 113708 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 103404 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 217112 # number of ReadSharedReq misses
|
|
system.l2c.InvalidateReq_misses::cpu0.data 236299 # number of InvalidateReq misses
|
|
system.l2c.InvalidateReq_misses::cpu1.data 242424 # number of InvalidateReq misses
|
|
system.l2c.InvalidateReq_misses::total 478723 # number of InvalidateReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 1049 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 1089 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 35955 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 271125 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 937 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.itb.walker 1064 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 35583 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 258093 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 604895 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 1049 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 1089 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 35955 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 271125 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 937 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.itb.walker 1064 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 35583 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 258093 # number of overall misses
|
|
system.l2c.overall_misses::total 604895 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 141902500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 151571500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 126127000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 145843500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 565444500 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 685542000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 674688000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 1360230000 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 79500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 20564235000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 20205053000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 40769288000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 4743421500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 4694333000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 9437754500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 15100537500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 13704189500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 28804727000 # number of ReadSharedReq miss cycles
|
|
system.l2c.InvalidateReq_miss_latency::cpu0.data 30754261500 # number of InvalidateReq miss cycles
|
|
system.l2c.InvalidateReq_miss_latency::cpu1.data 31540882000 # number of InvalidateReq miss cycles
|
|
system.l2c.InvalidateReq_miss_latency::total 62295143500 # number of InvalidateReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 141902500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 151571500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 4743421500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 35664772500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 126127000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.itb.walker 145843500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 4694333000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 33909242500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 79577214000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 141902500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 151571500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 4743421500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 35664772500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 126127000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.itb.walker 145843500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 4694333000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 33909242500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 79577214000 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 207802 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 158021 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 210447 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 159607 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 735877 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 7220092 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 7220092 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 20848 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 20725 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 41573 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 966133 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 929250 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 1895383 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 6712943 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 6662661 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 13375604 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 3071299 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 3032832 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 6104131 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::cpu0.data 611544 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::cpu1.data 610003 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::total 1221547 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 207802 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 158021 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 6712943 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 4037432 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 210447 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 159607 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 6662661 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 3962082 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 22110995 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 207802 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 158021 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 6712943 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 4037432 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 210447 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 159607 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 6662661 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 3962082 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 22110995 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.005048 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006891 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004452 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.006666 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.005625 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.785639 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.786055 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.785847 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.162935 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.166467 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.164666 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.005356 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005341 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.005348 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.037023 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.034095 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.035568 # miss rate for ReadSharedReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.386397 # miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.397414 # miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::total 0.391899 # miss rate for InvalidateReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.005048 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.006891 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.005356 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.067153 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004452 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.itb.walker 0.006666 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.005341 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.065141 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.027357 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.005048 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.006891 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.005356 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.067153 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004452 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.itb.walker 0.006666 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.005341 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.065141 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.027357 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 135274.070543 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 139184.113866 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 134607.257204 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 137070.958647 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 136613.795603 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 41854.936199 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41414.768891 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 41635.445363 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 130635.414218 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130617.257853 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 130626.415385 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 131926.616604 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131926.285024 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 131926.451676 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132801.012242 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 132530.554911 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 132672.201444 # average ReadSharedReq miss latency
|
|
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 130149.774227 # average InvalidateReq miss latency
|
|
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130106.268356 # average InvalidateReq miss latency
|
|
system.l2c.InvalidateReq_avg_miss_latency::total 130127.742975 # average InvalidateReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135274.070543 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 139184.113866 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 131926.616604 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 131543.651452 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 134607.257204 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 137070.958647 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 131926.285024 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 131383.813199 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 131555.417056 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135274.070543 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 139184.113866 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 131926.616604 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 131543.651452 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 134607.257204 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 137070.958647 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 131926.285024 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 131383.813199 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 131555.417056 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 840057 # number of writebacks
|
|
system.l2c.writebacks::total 840057 # number of writebacks
|
|
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1049 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1089 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 937 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1064 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 4139 # number of ReadReq MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::writebacks 995 # number of CleanEvict MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::total 995 # number of CleanEvict MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 16379 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 16291 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 32670 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 157417 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 154689 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 312106 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 35955 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 35583 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 71538 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 113708 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 103404 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 217112 # number of ReadSharedReq MSHR misses
|
|
system.l2c.InvalidateReq_mshr_misses::cpu0.data 236299 # number of InvalidateReq MSHR misses
|
|
system.l2c.InvalidateReq_mshr_misses::cpu1.data 242424 # number of InvalidateReq MSHR misses
|
|
system.l2c.InvalidateReq_mshr_misses::total 478723 # number of InvalidateReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1049 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.itb.walker 1089 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 35955 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 271125 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 937 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.itb.walker 1064 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 35583 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 258093 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 604895 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1049 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 1089 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 35955 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 271125 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 937 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.itb.walker 1064 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 35583 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 258093 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 604895 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 22063 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16577 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 21062 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17124 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 76826 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16927 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 16781 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 22063 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 33504 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 21062 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 33905 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 110534 # number of overall MSHR uncacheable misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 131412500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 140681500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 116757000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 135203500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 524054500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1157313500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1151117500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 2308431000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 69500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 18990065000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 18658163000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 37648228000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 4383871500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 4338503000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 8722374500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 13963457500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 12670149500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 26633607000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 28391271500 # number of InvalidateReq MSHR miss cycles
|
|
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 29116642000 # number of InvalidateReq MSHR miss cycles
|
|
system.l2c.InvalidateReq_mshr_miss_latency::total 57507913500 # number of InvalidateReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 131412500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140681500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 4383871500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 32953522500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 116757000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 135203500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 4338503000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 31328312500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 73528264000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 131412500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140681500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 4383871500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 32953522500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 116757000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 135203500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 4338503000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 31328312500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 73528264000 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2504708000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2630394000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2392752000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2780206500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 10308060500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2644060000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2792148000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 5436208000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2504708000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5274454000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2392752000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5572354500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 15744268500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005048 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006891 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004452 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.006666 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.005625 # mshr miss rate for ReadReq accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785639 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.786055 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.785847 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.162935 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.166467 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.164666 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005356 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005341 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005348 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.037023 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.034095 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.035568 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.386397 # mshr miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.397414 # mshr miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_mshr_miss_rate::total 0.391899 # mshr miss rate for InvalidateReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005048 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006891 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005356 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.067153 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004452 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.006666 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005341 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.065141 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.027357 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005048 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006891 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005356 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.067153 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004452 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.006666 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005341 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.065141 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.027357 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 125274.070543 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 129184.113866 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 124607.257204 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127070.958647 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 126613.795603 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70658.373527 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70659.720091 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70659.044995 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120635.414218 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120617.257853 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 120626.415385 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121926.616604 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121926.285024 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121926.451676 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122801.012242 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122530.554911 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122672.201444 # average ReadSharedReq mshr miss latency
|
|
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120149.774227 # average InvalidateReq mshr miss latency
|
|
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120106.268356 # average InvalidateReq mshr miss latency
|
|
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120127.742975 # average InvalidateReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125274.070543 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129184.113866 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121926.616604 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121543.651452 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124607.257204 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127070.958647 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121926.285024 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121383.813199 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 121555.417056 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125274.070543 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129184.113866 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121926.616604 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121543.651452 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124607.257204 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127070.958647 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121926.285024 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121383.813199 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 121555.417056 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113525.268549 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158677.324003 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113605.165701 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162357.305536 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 134174.114232 # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 156203.698234 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166387.462011 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 161273.525573 # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113525.268549 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157427.590735 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113605.165701 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 164351.998230 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 142438.240722 # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 76826 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 378489 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 33708 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 33708 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 946688 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 157044 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 33236 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 33237 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 790266 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 790266 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 301663 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6928 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3314453 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 3444143 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340891 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 340891 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 3785034 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 123230496 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 123400318 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7215296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 7215296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 130615614 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 3426 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 2449027 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 2449027 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 2449027 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 107350000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 5290500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 6222696821 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 6001448560 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 228378003 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
|
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
|
|
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
|
|
system.realview.ethernet.totPackets 3 # Total Packets
|
|
system.realview.ethernet.totBytes 966 # Total Bytes
|
|
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
|
system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
|
|
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
|
|
system.toL2Bus.snoop_filter.tot_requests 45764335 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 23167677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 1751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 2649 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 2649 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 1182601 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 20663192 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 8166804 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 15533735 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 41576 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 41577 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 1895383 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 1895383 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 13375604 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 6113005 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 1328211 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateResp 1221547 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40210956 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27881321 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 758327 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1083325 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 69933929 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 856211156 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 974300010 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2541024 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3345992 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 1836398182 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 1592965 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 47672379 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.011257 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.105498 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 47135748 98.87% 98.87% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 536631 1.13% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 47672379 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 30462031500 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 1592884 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 20106531000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 12681402468 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 440699000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 665076000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|