7433d77fcf
This patch adds the necessary commands and cache functionality to allow clean writebacks. This functionality is crucial, especially when having exclusive (victim) caches. For example, if read-only L1 instruction caches are not sending clean writebacks, there will never be any spills from the L1 to the L2. At the moment the cache model defaults to not sending clean writebacks, and this should possibly be re-evaluated. The implementation of clean writebacks relies on a new packet command WritebackClean, which acts much like a Writeback (renamed WritebackDirty), and also much like a CleanEvict. On eviction of a clean block the cache either sends a clean evict, or a clean writeback, and if any copies are still cached upstream the clean evict/writeback is dropped. Similarly, if a clean evict/writeback reaches a cache where there are outstanding MSHRs for the block, the packet is dropped. In the typical case though, the clean writeback allocates a block in the downstream cache, and marks it writable if the evicted block was writable. The patch changes the O3_ARM_v7a L1 cache configuration and the default L1 caches in config/common/Caches.py
96 lines
3.4 KiB
Python
96 lines
3.4 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Lisa Hsu
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from m5.objects import *
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# Base implementations of L1, L2, IO and TLB-walker caches. There are
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# used in the regressions and also as base components in the
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# system-configuration scripts. The values are meant to serve as a
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# starting point, and specific parameters can be overridden in the
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# specific instantiations.
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class L1Cache(Cache):
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assoc = 2
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hit_latency = 2
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response_latency = 2
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mshrs = 4
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tgts_per_mshr = 20
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class L1_ICache(L1Cache):
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is_read_only = True
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# Writeback clean lines as well
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writeback_clean = True
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class L1_DCache(L1Cache):
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pass
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class L2Cache(Cache):
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assoc = 8
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hit_latency = 20
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response_latency = 20
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mshrs = 20
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tgts_per_mshr = 12
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write_buffers = 8
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class IOCache(Cache):
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assoc = 8
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hit_latency = 50
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response_latency = 50
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mshrs = 20
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size = '1kB'
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tgts_per_mshr = 12
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forward_snoops = False
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class PageTableWalkerCache(Cache):
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assoc = 2
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hit_latency = 2
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response_latency = 2
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mshrs = 10
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size = '1kB'
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tgts_per_mshr = 12
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forward_snoops = False
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# the x86 table walker actually writes to the table-walker cache
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if buildEnv['TARGET_ISA'] == 'x86':
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is_read_only = False
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else:
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is_read_only = True
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# Writeback clean lines as well
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writeback_clean = True
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