3370059668
When in 64-bit mode, if the stack is accessed implicitly by an instruction, the alternate address prefix should be ignored if present. This patch adds an extra flag to the ldstop which signifies when the address override should be ignored. Then, for all of the affected instructions, this patch adds two options to the ld and st opcode to use the current stack addressing mode for all addresses and to ignore the AddressSizeFlagBit. Finally, this patch updates the x86 TLB to not truncate the address if it is in 64-bit mode and the IgnoreAddrSizeFlagBit is set. This fixes a problem when calling __libc_start_main with a binary that is linked with a recent version of ld. This version of ld uses the address override prefix (0x67) on the call instruction instead of a nop. Note: This has not been tested in compatibility mode and only the call instruction with the address override prefix has been tested. See [1] page 9 (pdf page 45) For instructions that are affected see [1] page 519 (pdf page 555). [1] http://support.amd.com/TechDocs/24594.pdf Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
773 lines
28 KiB
Plaintext
773 lines
28 KiB
Plaintext
// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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// Copyright (c) 2015 Advanced Micro Devices, Inc.
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// All rights reserved.
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2008 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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//////////////////////////////////////////////////////////////////////////
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//
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// LdStOp Microop templates
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//
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//////////////////////////////////////////////////////////////////////////
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// LEA template
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def template MicroLeaExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroLeaDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem, uint64_t setFlags,
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uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
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uint64_t _disp, InstRegIndex _segment,
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InstRegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize,
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Request::FlagsType _memFlags);
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%(BasicExecDeclare)s
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};
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}};
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// Load templates
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def template MicroLoadExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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fault = readMemAtomic(xc, traceData, EA, Mem,
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%(memDataSize)s, memFlags);
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if (fault == NoFault) {
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%(code)s;
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} else if (memFlags & Request::PREFETCH) {
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// For prefetches, ignore any faults/exceptions.
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return NoFault;
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}
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroLoadInitiateAcc {{
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Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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fault = initiateMemRead(xc, traceData, EA,
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%(memDataSize)s, memFlags);
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return fault;
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}
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}};
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def template MicroLoadCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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CPU_EXEC_CONTEXT * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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getMem(pkt, Mem, %(memDataSize)s, traceData);
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%(code)s;
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// Store templates
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def template MicroStoreExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT * xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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fault = writeMemAtomic(xc, traceData, Mem, %(memDataSize)s, EA,
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memFlags, NULL);
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template MicroStoreInitiateAcc {{
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Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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fault = writeMemTiming(xc, traceData, Mem, %(memDataSize)s, EA,
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memFlags, NULL);
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}
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return fault;
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}
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}};
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def template MicroStoreCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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CPU_EXEC_CONTEXT * xc, Trace::InstRecord * traceData) const
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{
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%(op_decl)s;
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%(op_rd)s;
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%(complete_code)s;
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%(op_wb)s;
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return NoFault;
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}
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}};
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// Common templates
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//This delcares the initiateAcc function in memory operations
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def template InitiateAccDeclare {{
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Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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//This declares the completeAcc function in memory operations
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def template CompleteAccDeclare {{
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Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template MicroLdStOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem, uint64_t setFlags,
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uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
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uint64_t _disp, InstRegIndex _segment,
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InstRegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize,
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Request::FlagsType _memFlags);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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// LdStSplitOp is a load or store that uses a pair of regs as the
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// source or destination. Used for cmpxchg{8,16}b.
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def template MicroLdStSplitOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem, uint64_t setFlags,
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uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
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uint64_t _disp, InstRegIndex _segment,
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InstRegIndex _dataLow, InstRegIndex _dataHi,
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uint8_t _dataSize, uint8_t _addressSize,
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Request::FlagsType _memFlags);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template MicroLdStOpConstructor {{
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%(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
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uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
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uint64_t _disp, InstRegIndex _segment,
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InstRegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize,
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Request::FlagsType _memFlags) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
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_scale, _index, _base,
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_disp, _segment, _data,
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_dataSize, _addressSize, _memFlags, %(op_class)s)
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{
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%(constructor)s;
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}
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}};
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def template MicroLdStSplitOpConstructor {{
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%(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
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uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
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uint64_t _disp, InstRegIndex _segment,
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InstRegIndex _dataLow, InstRegIndex _dataHi,
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uint8_t _dataSize, uint8_t _addressSize,
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Request::FlagsType _memFlags) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
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_scale, _index, _base,
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_disp, _segment, _dataLow, _dataHi,
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_dataSize, _addressSize, _memFlags, %(op_class)s)
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{
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%(constructor)s;
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}
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}};
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let {{
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class LdStOp(X86Microop):
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def __init__(self, data, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
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implicitStack):
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self.data = data
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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self.segment = segment
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self.dataSize = dataSize
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self.addressSize = addressSize
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self.memFlags = baseFlags
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if atCPL0:
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self.memFlags += " | (CPL0FlagBit << FlagShift)"
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self.instFlags = ""
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if prefetch:
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self.memFlags += " | Request::PREFETCH"
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self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
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if nonSpec:
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self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
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# For implicit stack operations, we should use *not* use the
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# alternative addressing mode for loads/stores if the prefix is set
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if not implicitStack:
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self.memFlags += " | (machInst.legacy.addr ? " + \
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"(AddrSizeFlagBit << FlagShift) : 0)"
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def getAllocator(self, microFlags):
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allocator = '''new %(class_name)s(machInst, macrocodeBlock,
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%(flags)s, %(scale)s, %(index)s, %(base)s,
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%(disp)s, %(segment)s, %(data)s,
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%(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags) + self.instFlags,
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"scale" : self.scale, "index" : self.index,
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"base" : self.base,
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"disp" : self.disp,
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"segment" : self.segment, "data" : self.data,
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"dataSize" : self.dataSize, "addressSize" : self.addressSize,
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"memFlags" : self.memFlags}
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return allocator
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class BigLdStOp(X86Microop):
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def __init__(self, data, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
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implicitStack):
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self.data = data
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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self.segment = segment
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self.dataSize = dataSize
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self.addressSize = addressSize
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self.memFlags = baseFlags
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if atCPL0:
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self.memFlags += " | (CPL0FlagBit << FlagShift)"
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self.instFlags = ""
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if prefetch:
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self.memFlags += " | Request::PREFETCH"
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self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
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if nonSpec:
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self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
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# For implicit stack operations, we should use *not* use the
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# alternative addressing mode for loads/stores if the prefix is set
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if not implicitStack:
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self.memFlags += " | (machInst.legacy.addr ? " + \
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"(AddrSizeFlagBit << FlagShift) : 0)"
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def getAllocator(self, microFlags):
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allocString = '''
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(%(dataSize)s >= 4) ?
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(StaticInstPtr)(new %(class_name)sBig(machInst,
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macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
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%(base)s, %(disp)s, %(segment)s, %(data)s,
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%(dataSize)s, %(addressSize)s, %(memFlags)s)) :
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(StaticInstPtr)(new %(class_name)s(machInst,
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macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
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%(base)s, %(disp)s, %(segment)s, %(data)s,
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%(dataSize)s, %(addressSize)s, %(memFlags)s))
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'''
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allocator = allocString % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags) + self.instFlags,
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"scale" : self.scale, "index" : self.index,
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"base" : self.base,
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"disp" : self.disp,
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"segment" : self.segment, "data" : self.data,
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"dataSize" : self.dataSize, "addressSize" : self.addressSize,
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"memFlags" : self.memFlags}
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return allocator
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class LdStSplitOp(LdStOp):
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def __init__(self, data, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
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implicitStack):
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super(LdStSplitOp, self).__init__(0, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
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implicitStack)
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(self.dataLow, self.dataHi) = data
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def getAllocator(self, microFlags):
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allocString = '''(StaticInstPtr)(new %(class_name)s(machInst,
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macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
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%(base)s, %(disp)s, %(segment)s,
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%(dataLow)s, %(dataHi)s,
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%(dataSize)s, %(addressSize)s, %(memFlags)s))
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'''
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allocator = allocString % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags) + self.instFlags,
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"scale" : self.scale, "index" : self.index,
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"base" : self.base,
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"disp" : self.disp,
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"segment" : self.segment,
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"dataLow" : self.dataLow, "dataHi" : self.dataHi,
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"dataSize" : self.dataSize, "addressSize" : self.addressSize,
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"memFlags" : self.memFlags}
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return allocator
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}};
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let {{
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# Make these empty strings so that concatenating onto
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# them will always work.
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header_output = ""
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decoder_output = ""
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exec_output = ""
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segmentEAExpr = \
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'bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);'
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calculateEA = 'EA = SegBase + ' + segmentEAExpr
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def defineMicroLoadOp(mnemonic, code, bigCode='',
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mem_flags="0", big=True, nonSpec=False,
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implicitStack=False):
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global header_output
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global decoder_output
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global exec_output
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global microopClasses
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Name = mnemonic
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name = mnemonic.lower()
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# Build up the all register version of this micro op
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iops = [InstObjParams(name, Name, 'X86ISA::LdStOp',
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{ "code": code,
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"ea_code": calculateEA,
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"memDataSize": "dataSize" })]
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if big:
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iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp',
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{ "code": bigCode,
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"ea_code": calculateEA,
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"memDataSize": "dataSize" })]
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for iop in iops:
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header_output += MicroLdStOpDeclare.subst(iop)
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decoder_output += MicroLdStOpConstructor.subst(iop)
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exec_output += MicroLoadExecute.subst(iop)
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exec_output += MicroLoadInitiateAcc.subst(iop)
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exec_output += MicroLoadCompleteAcc.subst(iop)
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if implicitStack:
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# For instructions that implicitly access the stack, the address
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# size is the same as the stack segment pointer size, not the
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# address size if specified by the instruction prefix
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addressSize = "env.stackSize"
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else:
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addressSize = "env.addressSize"
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base = LdStOp
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|
if big:
|
|
base = BigLdStOp
|
|
class LoadOp(base):
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
dataSize="env.dataSize",
|
|
addressSize=addressSize,
|
|
atCPL0=False, prefetch=False, nonSpec=nonSpec,
|
|
implicitStack=implicitStack):
|
|
super(LoadOp, self).__init__(data, segment, addr,
|
|
disp, dataSize, addressSize, mem_flags,
|
|
atCPL0, prefetch, nonSpec, implicitStack)
|
|
self.className = Name
|
|
self.mnemonic = name
|
|
|
|
microopClasses[name] = LoadOp
|
|
|
|
defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
|
|
'Data = Mem & mask(dataSize * 8);')
|
|
# Load micro-op used in macro-ops that implicitly access the stack
|
|
defineMicroLoadOp('Ld_stack', 'Data = merge(Data, Mem, dataSize);',
|
|
'Data = Mem & mask(dataSize * 8);',
|
|
implicitStack=True)
|
|
defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
|
|
'Data = Mem & mask(dataSize * 8);',
|
|
'(StoreCheck << FlagShift)')
|
|
defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
|
|
'Data = Mem & mask(dataSize * 8);',
|
|
'(StoreCheck << FlagShift) | Request::LOCKED_RMW',
|
|
nonSpec=True)
|
|
|
|
defineMicroLoadOp('Ldfp', code='FpData_uqw = Mem', big = False)
|
|
|
|
defineMicroLoadOp('Ldfp87', code='''
|
|
switch (dataSize)
|
|
{
|
|
case 4:
|
|
FpData_df = *(float *)&Mem;
|
|
break;
|
|
case 8:
|
|
FpData_df = *(double *)&Mem;
|
|
break;
|
|
default:
|
|
panic("Unhandled data size in LdFp87.\\n");
|
|
}
|
|
''', big = False)
|
|
|
|
# Load integer from memory into x87 top-of-stack register.
|
|
# Used to implement fild instruction.
|
|
defineMicroLoadOp('Ldifp87', code='''
|
|
switch (dataSize)
|
|
{
|
|
case 2:
|
|
FpData_df = (int64_t)sext<16>(Mem);
|
|
break;
|
|
case 4:
|
|
FpData_df = (int64_t)sext<32>(Mem);
|
|
break;
|
|
case 8:
|
|
FpData_df = (int64_t)Mem;
|
|
break;
|
|
default:
|
|
panic("Unhandled data size in LdIFp87.\\n");
|
|
}
|
|
''', big = False)
|
|
|
|
def defineMicroLoadSplitOp(mnemonic, code, mem_flags="0", nonSpec=False):
|
|
global header_output
|
|
global decoder_output
|
|
global exec_output
|
|
global microopClasses
|
|
Name = mnemonic
|
|
name = mnemonic.lower()
|
|
|
|
iop = InstObjParams(name, Name, 'X86ISA::LdStSplitOp',
|
|
{ "code": code,
|
|
"ea_code": calculateEA,
|
|
"memDataSize": "2 * dataSize" })
|
|
|
|
header_output += MicroLdStSplitOpDeclare.subst(iop)
|
|
decoder_output += MicroLdStSplitOpConstructor.subst(iop)
|
|
exec_output += MicroLoadExecute.subst(iop)
|
|
exec_output += MicroLoadInitiateAcc.subst(iop)
|
|
exec_output += MicroLoadCompleteAcc.subst(iop)
|
|
|
|
class LoadOp(LdStSplitOp):
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
dataSize="env.dataSize",
|
|
addressSize="env.addressSize",
|
|
atCPL0=False, prefetch=False, nonSpec=nonSpec,
|
|
implicitStack=False):
|
|
super(LoadOp, self).__init__(data, segment, addr,
|
|
disp, dataSize, addressSize, mem_flags,
|
|
atCPL0, prefetch, nonSpec, implicitStack)
|
|
self.className = Name
|
|
self.mnemonic = name
|
|
|
|
microopClasses[name] = LoadOp
|
|
|
|
code = '''
|
|
switch (dataSize) {
|
|
case 4:
|
|
DataLow = bits(Mem_u2qw[0], 31, 0);
|
|
DataHi = bits(Mem_u2qw[0], 63, 32);
|
|
break;
|
|
case 8:
|
|
DataLow = Mem_u2qw[0];
|
|
DataHi = Mem_u2qw[1];
|
|
break;
|
|
default:
|
|
panic("Unhandled data size %d in LdSplit.\\n", dataSize);
|
|
}'''
|
|
|
|
defineMicroLoadSplitOp('LdSplit', code,
|
|
'(StoreCheck << FlagShift)')
|
|
|
|
defineMicroLoadSplitOp('LdSplitl', code,
|
|
'(StoreCheck << FlagShift) | Request::LOCKED_RMW',
|
|
nonSpec=True)
|
|
|
|
def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0",
|
|
implicitStack=False):
|
|
global header_output
|
|
global decoder_output
|
|
global exec_output
|
|
global microopClasses
|
|
Name = mnemonic
|
|
name = mnemonic.lower()
|
|
|
|
# Build up the all register version of this micro op
|
|
iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
|
|
{ "code": code,
|
|
"complete_code": completeCode,
|
|
"ea_code": calculateEA,
|
|
"memDataSize": "dataSize" })
|
|
header_output += MicroLdStOpDeclare.subst(iop)
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
exec_output += MicroStoreExecute.subst(iop)
|
|
exec_output += MicroStoreInitiateAcc.subst(iop)
|
|
exec_output += MicroStoreCompleteAcc.subst(iop)
|
|
|
|
if implicitStack:
|
|
# For instructions that implicitly access the stack, the address
|
|
# size is the same as the stack segment pointer size, not the
|
|
# address size if specified by the instruction prefix
|
|
addressSize = "env.stackSize"
|
|
else:
|
|
addressSize = "env.addressSize"
|
|
|
|
class StoreOp(LdStOp):
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
dataSize="env.dataSize",
|
|
addressSize=addressSize,
|
|
atCPL0=False, nonSpec=False, implicitStack=implicitStack):
|
|
super(StoreOp, self).__init__(data, segment, addr, disp,
|
|
dataSize, addressSize, mem_flags, atCPL0, False,
|
|
nonSpec, implicitStack)
|
|
self.className = Name
|
|
self.mnemonic = name
|
|
|
|
microopClasses[name] = StoreOp
|
|
|
|
defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
|
|
# Store micro-op used in macro-ops that implicitly access the stack
|
|
defineMicroStoreOp('St_stack', 'Mem = pick(Data, 2, dataSize);',
|
|
implicitStack=True)
|
|
defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
|
|
mem_flags="Request::LOCKED_RMW")
|
|
|
|
defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;')
|
|
|
|
defineMicroStoreOp('Stfp87', code='''
|
|
switch (dataSize)
|
|
{
|
|
case 4: {
|
|
float single(FpData_df);
|
|
Mem = *(uint32_t *)&single;
|
|
} break;
|
|
case 8:
|
|
Mem = *(uint64_t *)&FpData_df;
|
|
break;
|
|
default:
|
|
panic("Unhandled data size in StFp87.\\n");
|
|
}
|
|
''')
|
|
|
|
defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
|
|
|
|
def defineMicroStoreSplitOp(mnemonic, code,
|
|
completeCode="", mem_flags="0"):
|
|
global header_output
|
|
global decoder_output
|
|
global exec_output
|
|
global microopClasses
|
|
Name = mnemonic
|
|
name = mnemonic.lower()
|
|
|
|
iop = InstObjParams(name, Name, 'X86ISA::LdStSplitOp',
|
|
{ "code": code,
|
|
"complete_code": completeCode,
|
|
"ea_code": calculateEA,
|
|
"memDataSize": "2 * dataSize" })
|
|
|
|
header_output += MicroLdStSplitOpDeclare.subst(iop)
|
|
decoder_output += MicroLdStSplitOpConstructor.subst(iop)
|
|
exec_output += MicroStoreExecute.subst(iop)
|
|
exec_output += MicroStoreInitiateAcc.subst(iop)
|
|
exec_output += MicroStoreCompleteAcc.subst(iop)
|
|
|
|
class StoreOp(LdStSplitOp):
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
dataSize="env.dataSize",
|
|
addressSize="env.addressSize",
|
|
atCPL0=False, nonSpec=False, implicitStack=False):
|
|
super(StoreOp, self).__init__(data, segment, addr, disp,
|
|
dataSize, addressSize, mem_flags, atCPL0, False,
|
|
nonSpec, implicitStack)
|
|
self.className = Name
|
|
self.mnemonic = name
|
|
|
|
microopClasses[name] = StoreOp
|
|
|
|
code = '''
|
|
switch (dataSize) {
|
|
case 4:
|
|
Mem_u2qw[0] = (DataHi << 32) | DataLow;
|
|
break;
|
|
case 8:
|
|
Mem_u2qw[0] = DataLow;
|
|
Mem_u2qw[1] = DataHi;
|
|
break;
|
|
default:
|
|
panic("Unhandled data size %d in StSplit.\\n", dataSize);
|
|
}'''
|
|
|
|
defineMicroStoreSplitOp('StSplit', code);
|
|
|
|
defineMicroStoreSplitOp('StSplitul', code,
|
|
mem_flags='Request::LOCKED_RMW')
|
|
|
|
iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
|
|
{ "code": "Data = merge(Data, EA, dataSize);",
|
|
"ea_code": "EA = " + segmentEAExpr,
|
|
"memDataSize": "dataSize" })
|
|
header_output += MicroLeaDeclare.subst(iop)
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
exec_output += MicroLeaExecute.subst(iop)
|
|
|
|
class LeaOp(LdStOp):
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
dataSize="env.dataSize", addressSize="env.addressSize"):
|
|
super(LeaOp, self).__init__(data, segment, addr, disp,
|
|
dataSize, addressSize, "0", False, False, False, False)
|
|
self.className = "Lea"
|
|
self.mnemonic = "lea"
|
|
|
|
microopClasses["lea"] = LeaOp
|
|
|
|
|
|
iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
|
|
{ "code": "xc->demapPage(EA, 0);",
|
|
"ea_code": calculateEA,
|
|
"memDataSize": "dataSize" })
|
|
header_output += MicroLeaDeclare.subst(iop)
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
exec_output += MicroLeaExecute.subst(iop)
|
|
|
|
class TiaOp(LdStOp):
|
|
def __init__(self, segment, addr, disp = 0,
|
|
dataSize="env.dataSize",
|
|
addressSize="env.addressSize"):
|
|
super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
|
|
addr, disp, dataSize, addressSize, "0", False, False,
|
|
False, False)
|
|
self.className = "Tia"
|
|
self.mnemonic = "tia"
|
|
|
|
microopClasses["tia"] = TiaOp
|
|
|
|
class CdaOp(LdStOp):
|
|
def __init__(self, segment, addr, disp = 0,
|
|
dataSize="env.dataSize",
|
|
addressSize="env.addressSize", atCPL0=False):
|
|
super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
|
|
addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
|
|
atCPL0, False, False, False)
|
|
self.className = "Cda"
|
|
self.mnemonic = "cda"
|
|
|
|
microopClasses["cda"] = CdaOp
|
|
}};
|