33683bd087
This patch is the eighth patch in a series adding RISC-V to gem5, and third of the bonus patches to the original series of five. It adds some regression tests to RISC-V. Regression tests included: - se/00.hello - se/02.insttest (split into several binaries which are not included due to large size) The tests added to 00.insttest will need to be build manually; to facilitate this, a Makefile is included. The required toolchain and compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools GitHub repository at https://github.com/riscv/riscv-tools. Note that because EBREAK only makes sense when gdb is running or while in FS mode, it is not included in the linux-rv64i insttest. ERET is not included because it does not make sense in SE mode and, in fact, causes a panic by design. Note also that not every system call is tested in linux-rv64i; of the ones defined in linux/process.hh, some have been given numbers but not definitions for the toolchain, or are merely stubs that always return 0. Of the ones that do work properly, only a subset are tested due to similar functionality. Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com>
324 lines
7.2 KiB
C++
324 lines
7.2 KiB
C++
/*
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* Copyright (c) 2016 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Alec Roelke
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*/
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#pragma once
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#include <cstdint>
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#include <limits>
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#include "insttest.h"
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namespace D
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{
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constexpr inline uint64_t
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bits(double d)
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{
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return reinterpret_cast<uint64_t&>(d);
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}
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constexpr inline double
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number(uint64_t b)
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{
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return reinterpret_cast<double&>(b);
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}
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inline bool
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isquietnan(double f)
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{
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return std::isnan(f) && (bits(f)&0x0008000000000000ULL) != 0;
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}
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inline bool
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issignalingnan(double f)
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{
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return std::isnan(f) && (bits(f)&0x0008000000000000ULL) == 0;
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}
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inline double
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load(double mem)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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asm volatile("fld %0,%1"
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: "=f" (fd)
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: "m" (mem));
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return fd;
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}
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inline double
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store(double fs)
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{
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double mem = std::numeric_limits<double>::signaling_NaN();
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asm volatile("fsd %1,%0" : "=m" (mem) : "f" (fs));
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return mem;
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}
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inline double
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fmadd_d(double fs1, double fs2, double fs3)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FR4OP("fmadd.d", fd, fs1, fs2, fs3);
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return fd;
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}
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inline double
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fmsub_d(double fs1, double fs2, double fs3)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FR4OP("fmsub.d", fd, fs1, fs2, fs3);
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return fd;
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}
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inline double
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fnmsub_d(double fs1, double fs2, double fs3)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FR4OP("fnmsub.d", fd, fs1, fs2, fs3);
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return fd;
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}
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inline double
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fnmadd_d(double fs1, double fs2, double fs3)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FR4OP("fnmadd.d", fd, fs1, fs2, fs3);
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return fd;
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}
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inline double
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fadd_d(double fs1, double fs2)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FROP("fadd.d", fd, fs1, fs2);
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return fd;
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}
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inline double
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fsub_d(double fs1, double fs2)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FROP("fsub.d", fd, fs1, fs2);
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return fd;
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}
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inline double
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fmul_d(double fs1, double fs2)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FROP("fmul.d", fd, fs1, fs2);
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return fd;
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}
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inline double
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fdiv_d(double fs1, double fs2)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FROP("fdiv.d", fd, fs1, fs2);
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return fd;
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}
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inline double
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fsqrt_d(double fs1)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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asm volatile("fsqrt.d %0,%1" : "=f" (fd) : "f" (fs1));
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return fd;
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}
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inline double
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fsgnj_d(double fs1, double fs2)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FROP("fsgnj.d", fd, fs1, fs2);
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return fd;
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}
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inline double
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fsgnjn_d(double fs1, double fs2)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FROP("fsgnjn.d", fd, fs1, fs2);
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return fd;
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}
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inline double
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fsgnjx_d(double fs1, double fs2)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FROP("fsgnjx.d", fd, fs1, fs2);
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return fd;
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}
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inline double
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fmin_d(double fs1, double fs2)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FROP("fmin.d", fd, fs1, fs2);
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return fd;
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}
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inline double
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fmax_d(double fs1, double fs2)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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FROP("fmax.d", fd, fs1, fs2);
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return fd;
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}
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inline float
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fcvt_s_d(double fs1)
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{
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float fd = std::numeric_limits<float>::signaling_NaN();
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asm volatile("fcvt.s.d %0,%1" : "=f" (fd) : "f" (fs1));
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return fd;
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}
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inline double
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fcvt_d_s(float fs1)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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asm volatile("fcvt.d.s %0,%1" : "=f" (fd) : "f" (fs1));
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return fd;
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}
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inline bool
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feq_d(double fs1, double fs2)
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{
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bool rd = false;
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asm volatile("feq.d %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2));
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return rd;
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}
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inline bool
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flt_d(double fs1, double fs2)
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{
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bool rd = false;
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asm volatile("flt.d %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2));
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return rd;
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}
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inline bool
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fle_d(double fs1, double fs2)
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{
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bool rd = false;
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asm volatile("fle.d %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2));
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return rd;
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}
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inline uint64_t
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fclass_d(double fs1)
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{
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uint64_t rd = -1;
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asm volatile("fclass.d %0,%1" : "=r" (rd) : "f" (fs1));
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return rd;
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}
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inline int64_t
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fcvt_w_d(double fs1)
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{
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int64_t rd = 0;
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asm volatile("fcvt.w.d %0,%1" : "=r" (rd) : "f" (fs1));
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return rd;
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}
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inline uint64_t
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fcvt_wu_d(double fs1)
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{
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uint64_t rd = 0;
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asm volatile("fcvt.wu.d %0,%1" : "=r" (rd) : "f" (fs1));
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return rd;
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}
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inline float
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fcvt_d_w(int64_t rs1)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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asm volatile("fcvt.d.w %0,%1" : "=f" (fd) : "r" (rs1));
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return fd;
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}
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inline double
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fcvt_d_wu(uint64_t rs1)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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asm volatile("fcvt.d.wu %0,%1" : "=f" (fd) : "r" (rs1));
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return fd;
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}
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inline int64_t
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fcvt_l_d(double fs1)
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{
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int64_t rd = 0;
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asm volatile("fcvt.l.d %0,%1" : "=r" (rd) : "f" (fs1));
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return rd;
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}
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inline uint64_t
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fcvt_lu_d(double fs1)
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{
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uint64_t rd = 0;
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asm volatile("fcvt.lu.d %0,%1" : "=r" (rd) : "f" (fs1));
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return rd;
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}
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inline uint64_t
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fmv_x_d(double fs1)
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{
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uint64_t rd = 0;
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asm volatile("fmv.x.d %0,%1" : "=r" (rd) : "f" (fs1));
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return rd;
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}
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inline double
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fcvt_d_l(int64_t rs1)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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asm volatile("fcvt.d.l %0,%1" : "=f" (fd) : "r" (rs1));
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return fd;
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}
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inline double
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fcvt_d_lu(uint64_t rs1)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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asm volatile("fcvt.d.lu %0,%1" : "=f" (fd) : "r" (rs1));
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return fd;
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}
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inline double
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fmv_d_x(uint64_t rs1)
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{
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double fd = std::numeric_limits<double>::signaling_NaN();
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asm volatile("fmv.d.x %0,%1" : "=f" (fd) : "r" (rs1));
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return fd;
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}
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} // namespace D
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