33683bd087
This patch is the eighth patch in a series adding RISC-V to gem5, and third of the bonus patches to the original series of five. It adds some regression tests to RISC-V. Regression tests included: - se/00.hello - se/02.insttest (split into several binaries which are not included due to large size) The tests added to 00.insttest will need to be build manually; to facilitate this, a Makefile is included. The required toolchain and compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools GitHub repository at https://github.com/riscv/riscv-tools. Note that because EBREAK only makes sense when gdb is running or while in FS mode, it is not included in the linux-rv64i insttest. ERET is not included because it does not make sense in SE mode and, in fact, causes a panic by design. Note also that not every system call is tested in linux-rv64i; of the ones defined in linux/process.hh, some have been given numbers but not definitions for the toolchain, or are merely stubs that always return 0. Of the ones that do work properly, only a subset are tested due to similar functionality. Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com>
300 lines
7.5 KiB
C++
300 lines
7.5 KiB
C++
/*
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* Copyright (c) 2016 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Alec Roelke
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*/
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#pragma once
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#include <cstdint>
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#include <tuple>
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#include "insttest.h"
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namespace A
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{
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inline int64_t
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lr_w(int32_t& mem)
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{
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int64_t r = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("lr.w %0,(%1)" : "=r" (r) : "r" (addr) : "memory");
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return r;
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}
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inline std::pair<int64_t, uint64_t>
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sc_w(int64_t rs2, int32_t& mem)
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{
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uint64_t addr = (uint64_t)&mem;
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uint64_t rd = -1;
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asm volatile("sc.w %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<int64_t, int64_t>
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amoswap_w(int64_t mem, int64_t rs2)
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{
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int64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amoswap.w %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<int64_t, int64_t>
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amoadd_w(int64_t mem, int64_t rs2)
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{
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int64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amoadd.w %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<uint64_t, uint64_t>
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amoxor_w(uint64_t mem, uint64_t rs2)
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{
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uint64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amoxor.w %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<uint64_t, uint64_t>
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amoand_w(uint64_t mem, uint64_t rs2)
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{
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uint64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amoand.w %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<uint64_t, uint64_t>
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amoor_w(uint64_t mem, uint64_t rs2)
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{
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uint64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amoor.w %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<int64_t, int64_t>
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amomin_w(int64_t mem, int64_t rs2)
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{
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int64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amomin.w %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<int64_t, int64_t>
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amomax_w(int64_t mem, int64_t rs2)
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{
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int64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amomax.w %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<uint64_t, uint64_t>
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amominu_w(uint64_t mem, uint64_t rs2)
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{
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uint64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amominu.w %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<uint64_t, uint64_t>
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amomaxu_w(uint64_t mem, uint64_t rs2)
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{
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uint64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amomaxu.w %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline int64_t
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lr_d(int64_t& mem)
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{
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int64_t r = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("lr.d %0,(%1)" : "=r" (r) : "r" (addr) : "memory");
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return r;
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}
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inline std::pair<int64_t, uint64_t>
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sc_d(int64_t rs2, int64_t& mem)
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{
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uint64_t addr = (uint64_t)&mem;
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uint64_t rd = -1;
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asm volatile("sc.d %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<int64_t, int64_t>
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amoswap_d(int64_t mem, int64_t rs2)
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{
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int64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amoswap.d %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<int64_t, int64_t>
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amoadd_d(int64_t mem, int64_t rs2)
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{
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int64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amoadd.d %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<uint64_t, uint64_t>
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amoxor_d(uint64_t mem, uint64_t rs2)
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{
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uint64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amoxor.d %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<uint64_t, uint64_t>
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amoand_d(uint64_t mem, uint64_t rs2)
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{
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uint64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amoand.d %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<uint64_t, uint64_t>
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amoor_d(uint64_t mem, uint64_t rs2)
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{
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uint64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amoor.d %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<int64_t, int64_t>
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amomin_d(int64_t mem, int64_t rs2)
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{
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int64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amomin.d %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<int64_t, int64_t>
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amomax_d(int64_t mem, int64_t rs2)
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{
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int64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amomax.d %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<uint64_t, uint64_t>
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amominu_d(uint64_t mem, uint64_t rs2)
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{
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uint64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amominu.d %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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inline std::pair<uint64_t, uint64_t>
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amomaxu_d(uint64_t mem, uint64_t rs2)
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{
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uint64_t rd = 0;
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uint64_t addr = (uint64_t)&mem;
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asm volatile("amomaxu.d %0,%2,(%1)"
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: "=r" (rd)
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: "r" (addr), "r" (rs2)
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: "memory");
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return {mem, rd};
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}
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} // namespace A
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