1780 lines
206 KiB
Text
1780 lines
206 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.966742 # Number of seconds simulated
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sim_ticks 1966741627000 # Number of ticks simulated
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final_tick 1966741627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1661877 # Simulator instruction rate (inst/s)
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host_op_rate 1661877 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 53617278530 # Simulator tick rate (ticks/s)
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host_mem_usage 335968 # Number of bytes of host memory used
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host_seconds 36.68 # Real time elapsed on the host
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sim_insts 60959478 # Number of instructions simulated
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sim_ops 60959478 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu0.inst 796480 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 24829632 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 62464 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 430848 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 26120384 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 796480 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 62464 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 858944 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7775296 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7775296 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.inst 12445 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 387963 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 976 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 6732 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 408131 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 121489 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 121489 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 404974 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 12624755 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 31760 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 219067 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13281045 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 404974 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 31760 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 436735 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3953390 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 3953390 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3953390 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 404974 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 12624755 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 31760 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 219067 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17234435 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 408131 # Number of read requests accepted
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system.physmem.writeReqs 121489 # Number of write requests accepted
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system.physmem.readBursts 408131 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 121489 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 26113216 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7773568 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 26120384 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7775296 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 25299 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25599 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25910 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25657 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25586 # Per bank write bursts
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system.physmem.perBankRdBursts::5 25177 # Per bank write bursts
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system.physmem.perBankRdBursts::6 26012 # Per bank write bursts
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system.physmem.perBankRdBursts::7 25110 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25002 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25326 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25348 # Per bank write bursts
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system.physmem.perBankRdBursts::11 25350 # Per bank write bursts
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system.physmem.perBankRdBursts::12 25736 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25396 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25673 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25838 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7888 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7973 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7891 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7697 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7528 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7375 # Per bank write bursts
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system.physmem.perBankWrBursts::6 8079 # Per bank write bursts
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system.physmem.perBankWrBursts::7 7030 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7056 # Per bank write bursts
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system.physmem.perBankWrBursts::9 7058 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7243 # Per bank write bursts
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system.physmem.perBankWrBursts::11 7671 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7657 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7555 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7813 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7948 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 71 # Number of times write queue was full causing retry
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system.physmem.totGap 1966734334500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 408131 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 121489 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 407926 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 1643 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::16 2752 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 5759 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 5841 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 6396 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 6541 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 7366 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 8415 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 6986 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 7365 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 8033 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 6912 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::28 7040 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 6284 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6217 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5993 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::32 5793 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 415 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::34 410 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 250 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 288 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 315 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 287 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 292 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 287 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 265 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 238 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 195 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 356 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 350 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 124 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 65984 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 513.560621 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 309.956643 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 413.656575 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 15493 23.48% 23.48% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::128-255 12381 18.76% 42.24% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::256-383 4640 7.03% 49.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 3311 5.02% 54.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 3269 4.95% 59.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 1542 2.34% 61.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 1639 2.48% 64.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1098 1.66% 65.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 22611 34.27% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 65984 # Bytes accessed per row activation
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|
system.physmem.rdPerTurnAround::samples 5405 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 75.487327 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 2871.274927 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-8191 5402 99.94% 99.94% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5405 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5405 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 22.472155 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::gmean 18.786030 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 24.242091 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-23 4888 90.43% 90.43% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-31 28 0.52% 90.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-39 175 3.24% 94.19% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-47 6 0.11% 94.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-55 5 0.09% 94.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-63 18 0.33% 94.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-71 9 0.17% 94.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-87 25 0.46% 95.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-95 5 0.09% 95.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-103 152 2.81% 98.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-111 23 0.43% 98.72% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-119 6 0.11% 98.83% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::168-175 6 0.11% 99.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-183 7 0.13% 99.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::184-191 9 0.17% 99.54% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::200-207 4 0.07% 99.74% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::216-223 6 0.11% 99.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-231 3 0.06% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5405 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 6252046750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 13902403000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2040095000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 15322.93 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 34072.93 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.13 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 365911 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 97586 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3713482.00 # Average gap between requests
|
|
system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 236241180 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 125565165 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 5643624480.000001 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 5139412980 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 370844640 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.actPowerDownEnergy 13440056220 # Energy for active power-down per rank (pJ)
|
|
system.physmem_0.prePowerDownEnergy 6440902560 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_0.selfRefreshEnergy 458973488295 # Energy for self refresh per rank (pJ)
|
|
system.physmem_0.totalEnergy 492152011950 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 250.237247 # Core power per rank (mW)
|
|
system.physmem_0.totalIdleTime 1954499558250 # Total Idle time Per DRAM Rank
|
|
system.physmem_0.memoryStateTime::IDLE 615960500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 2400520000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::SREF 1908253811750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 16773151500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 9224451750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 29473731500 # Time in different power states
|
|
system.physmem_1.actEnergy 234884580 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 124844115 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1454196660 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 313205220 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 5773313520.000001 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 5158429890 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 364374240 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.actPowerDownEnergy 13818451860 # Energy for active power-down per rank (pJ)
|
|
system.physmem_1.prePowerDownEnergy 6703686720 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_1.selfRefreshEnergy 458612092095 # Energy for self refresh per rank (pJ)
|
|
system.physmem_1.totalEnergy 492560034510 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 250.444709 # Core power per rank (mW)
|
|
system.physmem_1.totalIdleTime 1954406570250 # Total Idle time Per DRAM Rank
|
|
system.physmem_1.memoryStateTime::IDLE 598675750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 2455572000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::SREF 1906713566750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 17457468500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 9212976500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 30303367500 # Time in different power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.bridge.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu0.dtb.read_hits 7479115 # DTB read hits
|
|
system.cpu0.dtb.read_misses 7764 # DTB read misses
|
|
system.cpu0.dtb.read_acv 210 # DTB read access violations
|
|
system.cpu0.dtb.read_accesses 524068 # DTB read accesses
|
|
system.cpu0.dtb.write_hits 5079820 # DTB write hits
|
|
system.cpu0.dtb.write_misses 909 # DTB write misses
|
|
system.cpu0.dtb.write_acv 133 # DTB write access violations
|
|
system.cpu0.dtb.write_accesses 202594 # DTB write accesses
|
|
system.cpu0.dtb.data_hits 12558935 # DTB hits
|
|
system.cpu0.dtb.data_misses 8673 # DTB misses
|
|
system.cpu0.dtb.data_acv 343 # DTB access violations
|
|
system.cpu0.dtb.data_accesses 726662 # DTB accesses
|
|
system.cpu0.itb.fetch_hits 3638634 # ITB hits
|
|
system.cpu0.itb.fetch_misses 3984 # ITB misses
|
|
system.cpu0.itb.fetch_acv 184 # ITB acv
|
|
system.cpu0.itb.fetch_accesses 3642618 # ITB accesses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
|
system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions
|
|
system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::mean 272289101.854578 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::stdev 432882462.064242 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::min_value 249000 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateResidencyTicks::ON 116809469000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849932158000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.numCycles 3933483254 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed
|
|
system.cpu0.kern.inst.hwrei 163850 # number of hwrei instructions executed
|
|
system.cpu0.kern.ipl_count::0 56218 40.17% 40.17% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::total 139952 # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_good::0 55706 49.07% 49.07% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::31 55273 48.69% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::total 113518 # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_ticks::0 1903167810000 96.77% 96.77% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::21 93266000 0.00% 96.77% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::22 790441500 0.04% 96.81% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::30 321171500 0.02% 96.83% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::31 62368212000 3.17% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::total 1966740901000 # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_used::0 0.990893 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::31 0.680744 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::total 0.811121 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpctx 3064 2.07% 2.43% # number of callpals executed
|
|
system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpipl 133000 89.79% 92.25% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdusp 9 0.01% 96.66% # number of callpals executed
|
|
system.cpu0.kern.callpal::whami 2 0.00% 96.66% # number of callpals executed
|
|
system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed
|
|
system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed
|
|
system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::total 148125 # number of callpals executed
|
|
system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
|
system.cpu0.kern.mode_good::kernel 1368
|
|
system.cpu0.kern.mode_good::user 1369
|
|
system.cpu0.kern.mode_good::idle 0
|
|
system.cpu0.kern.mode_switch_good::kernel 0.195764 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::total 0.327510 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_ticks::kernel 1962821824500 99.80% 99.80% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::user 3919074500 0.20% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.swap_context 3065 # number of times the context was actually changed
|
|
system.cpu0.committedInsts 47690735 # Number of instructions committed
|
|
system.cpu0.committedOps 47690735 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 44243506 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 210072 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 1190980 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 5607273 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 44243506 # number of integer instructions
|
|
system.cpu0.num_fp_insts 210072 # number of float instructions
|
|
system.cpu0.num_int_register_reads 60857324 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 32955789 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 102653 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 104432 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 12599733 # number of memory refs
|
|
system.cpu0.num_load_insts 7506744 # Number of load instructions
|
|
system.cpu0.num_store_insts 5092989 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 3699864315.998118 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 233618938.001881 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.059392 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.940608 # Percentage of idle cycles
|
|
system.cpu0.Branches 7182999 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 2715471 5.69% 5.69% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 31387897 65.80% 71.50% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 52053 0.11% 71.61% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 26676 0.06% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMultAcc 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 1883 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMisc 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.66% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 7588274 15.91% 87.57% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 5010180 10.50% 98.08% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMemRead 92589 0.19% 98.27% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMemWrite 88924 0.19% 98.46% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 735804 1.54% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 47699751 # Class of executed instruction
|
|
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.dcache.tags.replacements 1183172 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 505.236482 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 11369674 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 1183684 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 9.605329 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.236482 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986790 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.986790 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 51472726 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 51472726 # Number of data accesses
|
|
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6400739 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 6400739 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 4669408 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 4669408 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146309 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 146309 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 11070147 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 11070147 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 11070147 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 11070147 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 938380 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 938380 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 255338 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 255338 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13584 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 13584 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1193718 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1193718 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1193718 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1193718 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31213946000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 31213946000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12660198000 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 12660198000 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149666500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 149666500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31954500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 31954500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 43874144000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 43874144000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 43874144000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 43874144000 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339119 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 7339119 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924746 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 4924746 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152578 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 152578 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152037 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 152037 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 12263865 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 12263865 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 12263865 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 12263865 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127860 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.127860 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051848 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.051848 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089030 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089030 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097336 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.097336 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097336 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.097336 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.652252 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.652252 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49582.114687 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 49582.114687 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11017.851885 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11017.851885 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.648743 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.648743 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 36754.194877 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 36754.194877 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.writebacks::writebacks 681271 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 681271 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938380 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 938380 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255338 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 255338 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13584 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13584 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193718 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 1193718 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193718 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 1193718 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30275566000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30275566000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12404860000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12404860000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136082500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136082500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26226500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26226500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42680426000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 42680426000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42680426000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 42680426000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572135500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572135500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572135500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572135500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127860 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127860 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051848 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051848 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089030 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089030 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.097336 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.097336 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.652252 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.652252 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48582.114687 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48582.114687 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10017.851885 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10017.851885 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.648743 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.648743 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.797964 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.797964 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.345021 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.345021 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.icache.tags.replacements 692001 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 47007113 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 692513 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 67.879033 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 44813245500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 48392391 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 48392391 # Number of data accesses
|
|
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 47007113 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 47007113 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 47007113 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 47007113 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 47007113 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 47007113 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 692639 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 692639 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 692639 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 692639 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 692639 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 692639 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10340404000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 10340404000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 10340404000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 10340404000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 10340404000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 10340404000 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 47699752 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 47699752 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 47699752 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 47699752 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 47699752 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 47699752 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.994758 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.994758 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 14928.994758 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 14928.994758 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.writebacks::writebacks 692001 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 692001 # number of writebacks
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692639 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 692639 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 692639 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 692639 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 692639 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 692639 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9647765000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 9647765000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9647765000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 9647765000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9647765000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 9647765000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.994758 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.read_hits 2442522 # DTB read hits
|
|
system.cpu1.dtb.read_misses 2621 # DTB read misses
|
|
system.cpu1.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu1.dtb.read_accesses 205338 # DTB read accesses
|
|
system.cpu1.dtb.write_hits 1749235 # DTB write hits
|
|
system.cpu1.dtb.write_misses 236 # DTB write misses
|
|
system.cpu1.dtb.write_acv 24 # DTB write access violations
|
|
system.cpu1.dtb.write_accesses 89740 # DTB write accesses
|
|
system.cpu1.dtb.data_hits 4191757 # DTB hits
|
|
system.cpu1.dtb.data_misses 2857 # DTB misses
|
|
system.cpu1.dtb.data_acv 24 # DTB access violations
|
|
system.cpu1.dtb.data_accesses 295078 # DTB accesses
|
|
system.cpu1.itb.fetch_hits 1826928 # ITB hits
|
|
system.cpu1.itb.fetch_misses 1064 # ITB misses
|
|
system.cpu1.itb.fetch_acv 0 # ITB acv
|
|
system.cpu1.itb.fetch_accesses 1827992 # ITB accesses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions
|
|
system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::mean 692202308.556150 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::stdev 417084374.205506 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::min_value 82000 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateResidencyTicks::ON 25114151500 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941627475500 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.numCycles 3931646339 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.hwrei 79700 # number of hwrei instructions executed
|
|
system.cpu1.kern.ipl_count::0 27196 38.42% 38.42% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::31 41097 58.06% 100.00% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::total 70787 # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_good::0 26331 48.20% 48.20% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::31 25806 47.24% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::total 54631 # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_ticks::0 1909855366000 97.15% 97.15% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::22 731068500 0.04% 97.19% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::30 371926000 0.02% 97.21% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::31 54864779000 2.79% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::total 1965823139500 # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_used::0 0.968194 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::31 0.627929 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::total 0.771766 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed
|
|
system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpipl 64567 88.14% 91.50% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed
|
|
system.cpu1.kern.callpal::whami 3 0.00% 94.69% # number of callpals executed
|
|
system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # number of callpals executed
|
|
system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
|
|
system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::total 73259 # number of callpals executed
|
|
system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::user 367 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches
|
|
system.cpu1.kern.mode_good::kernel 816
|
|
system.cpu1.kern.mode_good::user 367
|
|
system.cpu1.kern.mode_good::idle 449
|
|
system.cpu1.kern.mode_switch_good::kernel 0.415479 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_ticks::kernel 18376717500 0.94% 0.94% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::user 1492465500 0.08% 1.01% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::idle 1945081083000 98.99% 100.00% # number of ticks spent at the given mode
|
|
system.cpu1.kern.swap_context 2017 # number of times the context was actually changed
|
|
system.cpu1.committedInsts 13268743 # Number of instructions committed
|
|
system.cpu1.committedOps 13268743 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 12224543 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 423393 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 1315452 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 12224543 # number of integer instructions
|
|
system.cpu1.num_fp_insts 175144 # number of float instructions
|
|
system.cpu1.num_int_register_reads 16795911 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 8988763 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 4214824 # number of memory refs
|
|
system.cpu1.num_load_insts 2456352 # Number of load instructions
|
|
system.cpu1.num_store_insts 1758472 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 3881441492.340690 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 50204846.659310 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.012769 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.987231 # Percentage of idle cycles
|
|
system.cpu1.Branches 1899015 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 719201 5.42% 5.42% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 7861154 59.23% 64.65% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 22602 0.17% 64.82% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMultAcc 0 0.00% 64.92% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 1759 0.01% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMisc 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.94% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 2447876 18.44% 83.38% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 1681278 12.67% 96.05% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMemRead 81935 0.62% 96.67% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMemWrite 78198 0.59% 97.25% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 364369 2.75% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 13271624 # Class of executed instruction
|
|
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.dcache.tags.replacements 162095 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 484.320037 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 4015175 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 162424 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 24.720331 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 72635663500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320037 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 16996897 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 16996897 # Number of data accesses
|
|
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 2273870 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 2273870 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 1634166 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 1634166 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51918 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 51918 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52084 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 52084 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 3908036 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 3908036 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 3908036 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 3908036 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 118670 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 118670 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 58749 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 58749 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9148 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 9148 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6116 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 6116 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 177419 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 177419 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 177419 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 177419 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1466187000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 1466187000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1296760000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 1296760000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84020000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 84020000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34172000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 34172000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 2762947000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 2762947000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 2762947000 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 2762947000 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392540 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 2392540 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692915 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 1692915 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61066 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 61066 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58200 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 58200 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 4085455 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 4085455 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 4085455 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 4085455 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049600 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.049600 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034703 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.034703 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149805 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149805 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105086 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105086 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043427 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.043427 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043427 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.043427 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12355.161372 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12355.161372 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22072.886347 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22072.886347 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9184.521207 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9184.521207 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5587.311969 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5587.311969 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 15573.005146 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 15573.005146 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.writebacks::writebacks 111600 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 111600 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118670 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 118670 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58749 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 58749 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9148 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9148 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6116 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 6116 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 177419 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 177419 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 177419 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 177419 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1347517000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1347517000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238011000 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1238011000 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74872000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74872000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28056000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28056000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2585528000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 2585528000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2585528000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 2585528000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049600 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049600 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034703 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034703 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149805 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149805 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105086 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105086 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.043427 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.043427 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11355.161372 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11355.161372 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21072.886347 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21072.886347 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8184.521207 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8184.521207 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4587.311969 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4587.311969 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency
|
|
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.icache.tags.replacements 326538 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 445.783445 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 12944535 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 327049 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 39.579803 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 1960887554500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783445 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 13598713 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 13598713 # Number of data accesses
|
|
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 12944535 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 12944535 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 12944535 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 12944535 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 12944535 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 12944535 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 327089 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 327089 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 327089 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 327089 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 327089 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 327089 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4450039000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 4450039000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 4450039000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 4450039000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 4450039000 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 4450039000 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271624 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 13271624 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 13271624 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 13271624 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 13271624 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 13271624 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024646 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.024646 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024646 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.024646 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024646 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.024646 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13604.979073 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13604.979073 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13604.979073 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13604.979073 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.writebacks::writebacks 326538 # number of writebacks
|
|
system.cpu1.icache.writebacks::total 326538 # number of writebacks
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327089 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 327089 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 327089 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 327089 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 327089 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 327089 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4122950000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4122950000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4122950000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 4122950000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4122950000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 4122950000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024646 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.024646 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.024646 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12604.979073 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.iobus.trans_dist::ReadReq 7376 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7376 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 55675 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 55675 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14036 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 42642 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 126102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56144 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 82394 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 6051000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 216235265 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.iocache.tags.replacements 41698 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.568421 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1760410342000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 0.568421 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.035526 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.035526 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375570 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375570 # Number of data accesses
|
|
system.iocache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41730 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses
|
|
system.iocache.overall_misses::total 41730 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::tsunami.ide 4956087382 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 4956087382 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 4978500265 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 4978500265 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 4978500265 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 4978500265 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119274.340152 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 119274.340152 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 119302.666307 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 119302.666307 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 166.500000 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
|
system.iocache.writebacks::total 41520 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2876027417 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 2876027417 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 2889540300 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 2889540300 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 2889540300 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 2889540300 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69215.138068 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69215.138068 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency
|
|
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.l2c.tags.replacements 342937 # number of replacements
|
|
system.l2c.tags.tagsinuse 65389.954388 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 3989146 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 408458 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 9.766355 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 7750506000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 285.827023 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 4791.190703 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 59306.187710 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 166.825599 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 839.923352 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.073108 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.904941 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.002546 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.012816 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 697 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 35591920 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 35591920 # Number of data accesses
|
|
system.l2c.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.l2c.WritebackDirty_hits::writebacks 792871 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 792871 # number of WritebackDirty hits
|
|
system.l2c.WritebackClean_hits::writebacks 746791 # number of WritebackClean hits
|
|
system.l2c.WritebackClean_hits::total 746791 # number of WritebackClean hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 3150 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 2355 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 5505 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 947 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 959 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 1906 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 128503 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 43274 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 171777 # number of ReadExReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 680173 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 326101 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 1006274 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 663284 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 108416 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 771700 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 680173 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 791787 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 326101 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 151690 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1949751 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 680173 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 791787 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 326101 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 151690 # number of overall hits
|
|
system.l2c.overall_hits::total 1949751 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 1 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 116830 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 6419 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 123249 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 12445 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 987 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 13432 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 271517 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 340 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 271857 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 12445 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 388347 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 987 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 6759 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 408538 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 12445 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 388347 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 987 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 6759 # number of overall misses
|
|
system.l2c.overall_misses::total 408538 # number of overall misses
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 300000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 28500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 328500 # number of UpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 10622495500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 657559500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 11280055000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1281839000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 101239000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 1383078000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 21946509000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 42090000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 21988599000 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 1281839000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 32569004500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 101239000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 699649500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 34651732000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 1281839000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 32569004500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 101239000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 699649500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 34651732000 # number of overall miss cycles
|
|
system.l2c.WritebackDirty_accesses::writebacks 792871 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 792871 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::writebacks 746791 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::total 746791 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 3155 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 2356 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 5511 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 947 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 959 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 1906 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 245333 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 49693 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 295026 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 692618 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 327088 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 1019706 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 934801 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 108756 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 1043557 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 692618 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 1180134 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 327088 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 158449 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2358289 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 692618 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 1180134 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 327088 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 158449 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2358289 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001585 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000424 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.001089 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.476210 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.129173 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.417756 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.017968 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.003018 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.013172 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290454 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.003126 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.260510 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.017968 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.329070 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.003018 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.042657 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.173235 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.017968 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.329070 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.003018 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.042657 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.173235 # miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 60000 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 28500 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 54750 # average UpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90922.669691 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102439.554448 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 91522.486998 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 103000.321414 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 102572.441743 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 102968.880286 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80829.226163 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123794.117647 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 80882.960527 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 103000.321414 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 83865.729618 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 102572.441743 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 103513.759432 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 84818.871194 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 103000.321414 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 83865.729618 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 102572.441743 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 103513.759432 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 84818.871194 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.writebacks::writebacks 79969 # number of writebacks
|
|
system.l2c.writebacks::total 79969 # number of writebacks
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
|
|
system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 5 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 116830 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 6419 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 123249 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12445 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 976 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 13421 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271517 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 340 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 271857 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 12445 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 388347 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 976 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 6759 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 408527 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 12445 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 388347 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 976 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 6759 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 408527 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 7198 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 14123 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 21321 # number of overall MSHR uncacheable misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 250000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 268500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9454195500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 593369500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 10047565000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1157389000 # number of ReadCleanReq MSHR miss cycles
|
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system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 90609000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 1247998000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19231339000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 38690000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 19270029000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 1157389000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 28685534500 # number of demand (read+write) MSHR miss cycles
|
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system.l2c.demand_mshr_miss_latency::cpu1.inst 90609000 # number of demand (read+write) MSHR miss cycles
|
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system.l2c.demand_mshr_miss_latency::cpu1.data 632059500 # number of demand (read+write) MSHR miss cycles
|
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system.l2c.demand_mshr_miss_latency::total 30565592000 # number of demand (read+write) MSHR miss cycles
|
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system.l2c.overall_mshr_miss_latency::cpu0.inst 1157389000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 28685534500 # number of overall MSHR miss cycles
|
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system.l2c.overall_mshr_miss_latency::cpu1.inst 90609000 # number of overall MSHR miss cycles
|
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system.l2c.overall_mshr_miss_latency::cpu1.data 632059500 # number of overall MSHR miss cycles
|
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system.l2c.overall_mshr_miss_latency::total 30565592000 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1483681000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 24728000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 1508409000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1483681000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 24728000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 1508409000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.001585 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.000424 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.001089 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476210 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.129173 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.417756 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013162 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290454 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.003126 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260510 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.329070 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.042657 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.173230 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.329070 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.042657 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.173230 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80922.669691 # average ReadExReq mshr miss latency
|
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system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92439.554448 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 81522.486998 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92988.450935 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70829.226163 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113794.117647 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70882.960527 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency
|
|
system.membus.snoop_filter.tot_requests 856503 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 407142 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadReq 7198 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 292654 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 14123 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 14123 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 121489 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 262335 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 11693 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 9938 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 123969 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 123101 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 285456 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181120 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 1223762 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1307205 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31237440 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 31319834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 33978074 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 22774 # Total snoops (count)
|
|
system.membus.snoopTraffic 27264 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 493929 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0.001371 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0.036997 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 493252 99.86% 99.86% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 677 0.14% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 493929 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 40493000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1323047597 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2182313750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 915117 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.toL2Bus.snoop_filter.tot_requests 4789247 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 2394847 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 361788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 989 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 928 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2106871 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 872840 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackClean 1018539 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 815364 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 17050 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 11844 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 28894 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 297037 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 297037 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 1019728 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 1079947 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077258 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616236 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980715 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523549 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7197758 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88615616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119196292 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41832064 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17309590 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 266953562 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 403246 # Total snoops (count)
|
|
system.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes)
|
|
system.toL2Bus.snoop_fanout::samples 2790110 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.141029 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.348296 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 2396861 85.91% 85.91% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 393013 14.09% 99.99% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 235 0.01% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 2790110 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 4223757496 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 302383 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 1039141633 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 1817975093 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 491872018 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 276251327 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
|
|
|
|
---------- End Simulation Statistics ----------
|