aad02f8088
Special mpy importer is gone; everything is just plain
Python now (funky, but straight-up).
May not completely work yet... generates identical ini
files for many configs/kernel settings, but I have yet
to run it against regressions. This commit is for my
own convenience and won't be pushed until more testing
is done.
python/m5/__init__.py:
Get rid of mpy_importer and param_types.
python/m5/config.py:
Major cleanup. We now have separate classes and
instances for SimObjects. Proxy handling and param
conversion significantly reorganized. No explicit
instantiation step anymore; we can dump an ini file
straight from the original tree.
Still needs more/better/truer comments.
test/genini.py:
Replace LoadMpyFile() with built-in execfile().
Export __main__.m5_build_env.
python/m5/objects/AlphaConsole.py:
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/AlphaTLB.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/CoherenceProtocol.py:
python/m5/objects/Device.py:
python/m5/objects/DiskImage.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Ide.py:
python/m5/objects/IntrControl.py:
python/m5/objects/MemTest.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/Platform.py:
python/m5/objects/Process.py:
python/m5/objects/Repl.py:
python/m5/objects/Root.py:
python/m5/objects/SimConsole.py:
python/m5/objects/SimpleDisk.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
Fixes for eliminating mpy_importer, and modified
handling of frequency/latency params.
Also renamed parent to Parent.
--HG--
rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py
rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py
rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py
rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py
rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py
rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py
rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py
rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py
extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76
52 lines
2.3 KiB
Python
52 lines
2.3 KiB
Python
from m5 import *
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from Device import FooPioDevice, DmaDevice
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class PciConfigData(SimObject):
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type = 'PciConfigData'
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VendorID = Param.UInt16("Vendor ID")
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DeviceID = Param.UInt16("Device ID")
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Command = Param.UInt16(0, "Command")
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Status = Param.UInt16(0, "Status")
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Revision = Param.UInt8(0, "Device")
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ProgIF = Param.UInt8(0, "Programming Interface")
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SubClassCode = Param.UInt8(0, "Sub-Class Code")
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ClassCode = Param.UInt8(0, "Class Code")
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CacheLineSize = Param.UInt8(0, "System Cacheline Size")
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LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
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HeaderType = Param.UInt8(0, "PCI Header Type")
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BIST = Param.UInt8(0, "Built In Self Test")
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BAR0 = Param.UInt32(0x00, "Base Address Register 0")
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BAR1 = Param.UInt32(0x00, "Base Address Register 1")
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BAR2 = Param.UInt32(0x00, "Base Address Register 2")
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BAR3 = Param.UInt32(0x00, "Base Address Register 3")
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BAR4 = Param.UInt32(0x00, "Base Address Register 4")
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BAR5 = Param.UInt32(0x00, "Base Address Register 5")
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BAR0Size = Param.UInt32(0, "Base Address Register 0 Size")
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BAR1Size = Param.UInt32(0, "Base Address Register 1 Size")
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BAR2Size = Param.UInt32(0, "Base Address Register 2 Size")
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BAR3Size = Param.UInt32(0, "Base Address Register 3 Size")
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BAR4Size = Param.UInt32(0, "Base Address Register 4 Size")
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BAR5Size = Param.UInt32(0, "Base Address Register 5 Size")
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CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
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SubsystemID = Param.UInt16(0x00, "Subsystem ID")
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SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
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ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
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InterruptLine = Param.UInt8(0x00, "Interrupt Line")
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InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
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MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
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MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
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class PciConfigAll(FooPioDevice):
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type = 'PciConfigAll'
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class PciDevice(DmaDevice):
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type = 'PciDevice'
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abstract = True
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addr = 0xffffffffL
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pci_bus = Param.Int("PCI bus")
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pci_dev = Param.Int("PCI device number")
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pci_func = Param.Int("PCI function code")
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configdata = Param.PciConfigData(Parent.any, "PCI Config data")
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configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
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