a317764577
This patch is imported from reviewboard patch 2551 by Nilay. This patch moves from a dynamically defined MachineType to a statically defined one. The need for this patch was felt since a dynamically defined type prevents us from having types for which no machine definition may exist. The following changes have been made: i. each machine definition now uses a type from the MachineType enumeration instead of any random identifier. This required changing the grammar and the *.sm files. ii. MachineType enumeration defined statically in RubySlicc_Exports.sm. * * * normal protocol fixes for nilay's parser machine type fix
520 lines
16 KiB
Plaintext
520 lines
16 KiB
Plaintext
/*
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* Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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machine(MachineType:Directory, "MESI Two Level directory protocol")
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: DirectoryMemory * directory;
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Cycles to_mem_ctrl_latency := 1;
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Cycles directory_latency := 6;
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MessageBuffer * requestToDir, network="From", virtual_network="0",
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vnet_type="request";
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MessageBuffer * responseToDir, network="From", virtual_network="1",
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vnet_type="response";
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MessageBuffer * responseFromDir, network="To", virtual_network="1",
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vnet_type="response";
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MessageBuffer * responseFromMemory;
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{
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// STATES
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state_declaration(State, desc="Directory states", default="Directory_State_I") {
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// Base states
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I, AccessPermission:Read_Write, desc="dir is the owner and memory is up-to-date, all other copies are Invalid";
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ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when in I";
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ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when in I";
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M, AccessPermission:Maybe_Stale, desc="memory copy may be stale, i.e. other modified copies may exist";
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IM, AccessPermission:Busy, desc="Intermediate State I>M";
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MI, AccessPermission:Busy, desc="Intermediate State M>I";
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M_DRD, AccessPermission:Busy, desc="Intermediate State when there is a dma read";
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M_DRDI, AccessPermission:Busy, desc="Intermediate State when there is a dma read";
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M_DWR, AccessPermission:Busy, desc="Intermediate State when there is a dma write";
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M_DWRI, AccessPermission:Busy, desc="Intermediate State when there is a dma write";
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}
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// Events
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enumeration(Event, desc="Directory events") {
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Fetch, desc="A memory fetch arrives";
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Data, desc="writeback data arrives";
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Memory_Data, desc="Fetched data from memory arrives";
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Memory_Ack, desc="Writeback Ack from memory arrives";
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//added by SS for dma
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DMA_READ, desc="A DMA Read memory request";
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DMA_WRITE, desc="A DMA Write memory request";
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CleanReplacement, desc="Clean Replacement in L2 cache";
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}
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// TYPES
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// DirectoryEntry
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structure(Entry, desc="...", interface="AbstractEntry") {
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State DirectoryState, desc="Directory state";
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MachineID Owner;
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}
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// TBE entries for DMA requests
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structure(TBE, desc="TBE entries for outstanding DMA requests") {
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Addr PhysicalAddress, desc="physical address";
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State TBEState, desc="Transient State";
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DataBlock DataBlk, desc="Data to be written (DMA write only)";
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int Len, desc="...";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Addr);
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void allocate(Addr);
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void deallocate(Addr);
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bool isPresent(Addr);
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bool functionalRead(Packet *pkt);
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int functionalWrite(Packet *pkt);
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}
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// ** OBJECTS **
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TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
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Tick clockEdge();
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Tick cyclesToTicks(Cycles c);
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void set_tbe(TBE tbe);
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void unset_tbe();
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void wakeUpBuffers(Addr a);
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Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
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Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
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if (is_valid(dir_entry)) {
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return dir_entry;
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}
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dir_entry := static_cast(Entry, "pointer",
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directory.allocate(addr, new Entry));
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return dir_entry;
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}
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State getState(TBE tbe, Addr addr) {
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if (is_valid(tbe)) {
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return tbe.TBEState;
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} else if (directory.isPresent(addr)) {
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return getDirectoryEntry(addr).DirectoryState;
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} else {
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return State:I;
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}
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}
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void setState(TBE tbe, Addr addr, State state) {
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (directory.isPresent(addr)) {
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getDirectoryEntry(addr).DirectoryState := state;
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}
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}
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AccessPermission getAccessPermission(Addr addr) {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(tbe.TBEState));
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return Directory_State_to_permission(tbe.TBEState);
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}
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if(directory.isPresent(addr)) {
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DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState));
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return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
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}
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DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
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return AccessPermission:NotPresent;
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}
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void functionalRead(Addr addr, Packet *pkt) {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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testAndRead(addr, tbe.DataBlk, pkt);
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} else {
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functionalMemoryRead(pkt);
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}
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}
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int functionalWrite(Addr addr, Packet *pkt) {
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int num_functional_writes := 0;
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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num_functional_writes := num_functional_writes +
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testAndWrite(addr, tbe.DataBlk, pkt);
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}
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num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
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return num_functional_writes;
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}
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void setAccessPermission(Addr addr, State state) {
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if (directory.isPresent(addr)) {
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getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
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}
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}
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bool isGETRequest(CoherenceRequestType type) {
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return (type == CoherenceRequestType:GETS) ||
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(type == CoherenceRequestType:GET_INSTR) ||
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(type == CoherenceRequestType:GETX);
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}
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// ** OUT_PORTS **
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out_port(responseNetwork_out, ResponseMsg, responseFromDir);
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// ** IN_PORTS **
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in_port(requestNetwork_in, RequestMsg, requestToDir, rank = 0) {
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if (requestNetwork_in.isReady(clockEdge())) {
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peek(requestNetwork_in, RequestMsg) {
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assert(in_msg.Destination.isElement(machineID));
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if (isGETRequest(in_msg.Type)) {
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trigger(Event:Fetch, in_msg.addr, TBEs[in_msg.addr]);
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} else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
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trigger(Event:DMA_READ, makeLineAddress(in_msg.addr),
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TBEs[makeLineAddress(in_msg.addr)]);
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} else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
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trigger(Event:DMA_WRITE, makeLineAddress(in_msg.addr),
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TBEs[makeLineAddress(in_msg.addr)]);
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} else {
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DPRINTF(RubySlicc, "%s\n", in_msg);
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error("Invalid message");
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}
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}
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}
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}
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in_port(responseNetwork_in, ResponseMsg, responseToDir, rank = 1) {
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if (responseNetwork_in.isReady(clockEdge())) {
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peek(responseNetwork_in, ResponseMsg) {
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assert(in_msg.Destination.isElement(machineID));
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if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
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trigger(Event:Data, in_msg.addr, TBEs[in_msg.addr]);
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} else if (in_msg.Type == CoherenceResponseType:ACK) {
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trigger(Event:CleanReplacement, in_msg.addr, TBEs[in_msg.addr]);
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} else {
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DPRINTF(RubySlicc, "%s\n", in_msg.Type);
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error("Invalid message");
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}
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}
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}
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}
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// off-chip memory request/response is done
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in_port(memQueue_in, MemoryMsg, responseFromMemory, rank = 2) {
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if (memQueue_in.isReady(clockEdge())) {
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peek(memQueue_in, MemoryMsg) {
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if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
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trigger(Event:Memory_Data, in_msg.addr, TBEs[in_msg.addr]);
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} else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
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trigger(Event:Memory_Ack, in_msg.addr, TBEs[in_msg.addr]);
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} else {
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DPRINTF(RubySlicc, "%s\n", in_msg.Type);
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error("Invalid message");
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}
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}
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}
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}
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// Actions
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action(a_sendAck, "a", desc="Send ack to L2") {
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peek(responseNetwork_in, ResponseMsg) {
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enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:MEMORY_ACK;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.Sender);
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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}
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action(d_sendData, "d", desc="Send data to requestor") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:MEMORY_DATA;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.OriginalRequestorMachId);
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.Dirty := false;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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Entry e := getDirectoryEntry(in_msg.addr);
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e.Owner := in_msg.OriginalRequestorMachId;
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}
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}
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}
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// Actions
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action(aa_sendAck, "aa", desc="Send ack to L2") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:MEMORY_ACK;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.OriginalRequestorMachId);
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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}
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action(j_popIncomingRequestQueue, "j", desc="Pop incoming request queue") {
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requestNetwork_in.dequeue(clockEdge());
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}
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action(k_popIncomingResponseQueue, "k", desc="Pop incoming request queue") {
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responseNetwork_in.dequeue(clockEdge());
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}
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action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
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memQueue_in.dequeue(clockEdge());
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}
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action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
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wakeUpBuffers(address);
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}
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action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
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peek(requestNetwork_in, RequestMsg) {
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queueMemoryRead(in_msg.Requestor, address, to_mem_ctrl_latency);
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}
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}
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action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
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peek(responseNetwork_in, ResponseMsg) {
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queueMemoryWrite(in_msg.Sender, address, to_mem_ctrl_latency,
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in_msg.DataBlk);
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}
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}
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//added by SS for dma
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action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
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peek(requestNetwork_in, RequestMsg) {
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queueMemoryRead(in_msg.Requestor, address, to_mem_ctrl_latency);
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}
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}
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action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
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requestNetwork_in.dequeue(clockEdge());
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}
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action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(qw_queueMemoryWBRequest_partial, "qwp",
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desc="Queue off-chip writeback request") {
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peek(requestNetwork_in, RequestMsg) {
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queueMemoryWritePartial(machineID, address, to_mem_ctrl_latency,
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in_msg.DataBlk, in_msg.Len);
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}
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}
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action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
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enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:ACK;
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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action(z_stallAndWaitRequest, "z", desc="recycle request queue") {
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stall_and_wait(requestNetwork_in, address);
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}
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action(zz_recycleDMAQueue, "zz", desc="recycle DMA queue") {
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requestNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
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}
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action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
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peek(requestNetwork_in, RequestMsg) {
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enqueue(responseNetwork_out, ResponseMsg, directory_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:INV;
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out_msg.Sender := machineID;
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out_msg.Destination.add(getDirectoryEntry(address).Owner);
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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}
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action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
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peek(responseNetwork_in, ResponseMsg) {
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enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(v_allocateTBE, "v", desc="Allocate TBE") {
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peek(requestNetwork_in, RequestMsg) {
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TBEs.allocate(address);
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set_tbe(TBEs[address]);
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tbe.DataBlk := in_msg.DataBlk;
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tbe.PhysicalAddress := in_msg.addr;
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tbe.Len := in_msg.Len;
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}
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}
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action(qw_queueMemoryWBRequest_partialTBE, "qwt",
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desc="Queue off-chip writeback request") {
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peek(responseNetwork_in, ResponseMsg) {
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queueMemoryWritePartial(in_msg.Sender, tbe.PhysicalAddress,
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to_mem_ctrl_latency, tbe.DataBlk, tbe.Len);
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}
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}
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action(w_deallocateTBE, "w", desc="Deallocate TBE") {
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TBEs.deallocate(address);
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unset_tbe();
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}
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// TRANSITIONS
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transition(I, Fetch, IM) {
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qf_queueMemoryFetchRequest;
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j_popIncomingRequestQueue;
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}
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transition(M, Fetch) {
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inv_sendCacheInvalidate;
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z_stallAndWaitRequest;
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}
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transition(IM, Memory_Data, M) {
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d_sendData;
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l_popMemQueue;
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kd_wakeUpDependents;
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}
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//added by SS
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transition(M, CleanReplacement, I) {
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a_sendAck;
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k_popIncomingResponseQueue;
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kd_wakeUpDependents;
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}
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transition(M, Data, MI) {
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qw_queueMemoryWBRequest;
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k_popIncomingResponseQueue;
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}
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transition(MI, Memory_Ack, I) {
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aa_sendAck;
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l_popMemQueue;
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kd_wakeUpDependents;
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}
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//added by SS for dma support
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transition(I, DMA_READ, ID) {
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qf_queueMemoryFetchRequestDMA;
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j_popIncomingRequestQueue;
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}
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transition(ID, Memory_Data, I) {
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dr_sendDMAData;
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l_popMemQueue;
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kd_wakeUpDependents;
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}
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transition(I, DMA_WRITE, ID_W) {
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qw_queueMemoryWBRequest_partial;
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j_popIncomingRequestQueue;
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}
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transition(ID_W, Memory_Ack, I) {
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da_sendDMAAck;
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l_popMemQueue;
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kd_wakeUpDependents;
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}
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transition({ID, ID_W, M_DRDI, M_DWRI, IM, MI}, {Fetch, Data} ) {
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z_stallAndWaitRequest;
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}
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transition({ID, ID_W, M_DRD, M_DRDI, M_DWR, M_DWRI, IM, MI}, {DMA_WRITE, DMA_READ} ) {
|
|
zz_recycleDMAQueue;
|
|
}
|
|
|
|
|
|
transition(M, DMA_READ, M_DRD) {
|
|
inv_sendCacheInvalidate;
|
|
j_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(M_DRD, Data, M_DRDI) {
|
|
drp_sendDMAData;
|
|
qw_queueMemoryWBRequest;
|
|
k_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(M_DRDI, Memory_Ack, I) {
|
|
aa_sendAck;
|
|
l_popMemQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(M, DMA_WRITE, M_DWR) {
|
|
v_allocateTBE;
|
|
inv_sendCacheInvalidate;
|
|
j_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(M_DWR, Data, M_DWRI) {
|
|
qw_queueMemoryWBRequest_partialTBE;
|
|
k_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(M_DWRI, Memory_Ack, I) {
|
|
aa_sendAck;
|
|
da_sendDMAAck;
|
|
w_deallocateTBE;
|
|
l_popMemQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
}
|