1200 lines
37 KiB
Plaintext
1200 lines
37 KiB
Plaintext
/*
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* Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lisa Hsu
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*/
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machine(MachineType:TCC, "TCC Cache")
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: CacheMemory * L2cache;
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WireBuffer * w_reqToTCCDir;
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WireBuffer * w_respToTCCDir;
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WireBuffer * w_TCCUnblockToTCCDir;
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WireBuffer * w_reqToTCC;
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WireBuffer * w_probeToTCC;
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WireBuffer * w_respToTCC;
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int TCC_select_num_bits;
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Cycles l2_request_latency := 1;
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Cycles l2_response_latency := 20;
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// To the general response network
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MessageBuffer * responseFromTCC, network="To", virtual_network="3", vnet_type="response";
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// From the general response network
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MessageBuffer * responseToTCC, network="From", virtual_network="3", vnet_type="response";
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{
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// EVENTS
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enumeration(Event, desc="TCC Events") {
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// Requests coming from the Cores
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RdBlk, desc="CPU RdBlk event";
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RdBlkM, desc="CPU RdBlkM event";
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RdBlkS, desc="CPU RdBlkS event";
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CtoD, desc="Change to Dirty request";
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WrVicBlk, desc="L1 Victim (dirty)";
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WrVicBlkShared, desc="L1 Victim (dirty)";
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ClVicBlk, desc="L1 Victim (clean)";
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ClVicBlkShared, desc="L1 Victim (clean)";
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CPUData, desc="WB data from CPU";
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CPUDataShared, desc="WB data from CPU, NBReqShared 1";
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StaleWB, desc="Stale WB, No data";
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L2_Repl, desc="L2 Replacement";
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// Probes
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PrbInvData, desc="Invalidating probe, return dirty data";
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PrbInv, desc="Invalidating probe, no need to return data";
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PrbShrData, desc="Downgrading probe, return data";
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// Coming from Memory Controller
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WBAck, desc="ack from memory";
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CancelWB, desc="Cancel WB from L2";
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}
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// STATES
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state_declaration(State, desc="TCC State", default="TCC_State_I") {
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M, AccessPermission:Read_Write, desc="Modified"; // No other cache has copy, memory stale
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O, AccessPermission:Read_Only, desc="Owned"; // Correct most recent copy, others may exist in S
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E, AccessPermission:Read_Write, desc="Exclusive"; // Correct, most recent, and only copy (and == Memory)
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S, AccessPermission:Read_Only, desc="Shared"; // Correct, most recent. If no one in O, then == Memory
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I, AccessPermission:Invalid, desc="Invalid";
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I_M, AccessPermission:Busy, desc="Invalid, received WrVicBlk, sent Ack, waiting for Data";
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I_O, AccessPermission:Busy, desc="Invalid, received WrVicBlk, sent Ack, waiting for Data";
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I_E, AccessPermission:Busy, desc="Invalid, receive ClVicBlk, sent Ack, waiting for Data";
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I_S, AccessPermission:Busy, desc="Invalid, receive ClVicBlk, sent Ack, waiting for Data";
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S_M, AccessPermission:Busy, desc="received WrVicBlk, sent Ack, waiting for Data, then go to M";
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S_O, AccessPermission:Busy, desc="received WrVicBlkShared, sent Ack, waiting for Data, then go to O";
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S_E, AccessPermission:Busy, desc="Shared, received ClVicBlk, sent Ack, waiting for Data, then go to E";
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S_S, AccessPermission:Busy, desc="Shared, received ClVicBlk, sent Ack, waiting for Data, then go to S";
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E_M, AccessPermission:Busy, desc="received WrVicBlk, sent Ack, waiting for Data, then go to O";
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E_O, AccessPermission:Busy, desc="received WrVicBlkShared, sent Ack, waiting for Data, then go to O";
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E_E, AccessPermission:Busy, desc="received WrVicBlk, sent Ack, waiting for Data, then go to O";
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E_S, AccessPermission:Busy, desc="Shared, received WrVicBlk, sent Ack, waiting for Data";
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O_M, AccessPermission:Busy, desc="...";
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O_O, AccessPermission:Busy, desc="...";
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O_E, AccessPermission:Busy, desc="...";
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M_M, AccessPermission:Busy, desc="...";
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M_O, AccessPermission:Busy, desc="...";
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M_E, AccessPermission:Busy, desc="...";
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M_S, AccessPermission:Busy, desc="...";
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D_I, AccessPermission:Invalid, desc="drop WB data on the floor when receive";
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MOD_I, AccessPermission:Busy, desc="drop WB data on the floor, waiting for WBAck from Mem";
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MO_I, AccessPermission:Busy, desc="M or O, received L2_Repl, waiting for WBAck from Mem";
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ES_I, AccessPermission:Busy, desc="E or S, received L2_Repl, waiting for WBAck from Mem";
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I_C, AccessPermission:Invalid, desc="sent cancel, just waiting to receive mem wb ack so nothing gets confused";
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}
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enumeration(RequestType, desc="To communicate stats from transitions to recordStats") {
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DataArrayRead, desc="Read the data array";
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DataArrayWrite, desc="Write the data array";
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TagArrayRead, desc="Read the data array";
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TagArrayWrite, desc="Write the data array";
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}
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// STRUCTURES
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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State CacheState, desc="cache state";
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bool Dirty, desc="Is the data dirty (diff from memory?)";
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DataBlock DataBlk, desc="Data for the block";
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}
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structure(TBE, desc="...") {
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="data for the block";
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bool Dirty, desc="Is the data dirty?";
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bool Shared, desc="Victim hit by shared probe";
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MachineID From, desc="Waiting for writeback from...";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Addr);
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void allocate(Addr);
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void deallocate(Addr);
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bool isPresent(Addr);
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}
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TBETable TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs";
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int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
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void set_cache_entry(AbstractCacheEntry b);
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void unset_cache_entry();
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void set_tbe(TBE b);
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void unset_tbe();
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void wakeUpAllBuffers();
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void wakeUpBuffers(Addr a);
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// FUNCTION DEFINITIONS
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Tick clockEdge();
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Tick cyclesToTicks(Cycles c);
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Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
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return static_cast(Entry, "pointer", L2cache.lookup(addr));
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}
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DataBlock getDataBlock(Addr addr), return_by_ref="yes" {
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return getCacheEntry(addr).DataBlk;
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}
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bool presentOrAvail(Addr addr) {
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return L2cache.isTagPresent(addr) || L2cache.cacheAvail(addr);
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}
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State getState(TBE tbe, Entry cache_entry, Addr addr) {
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if (is_valid(tbe)) {
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return tbe.TBEState;
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} else if (is_valid(cache_entry)) {
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return cache_entry.CacheState;
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}
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return State:I;
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}
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void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (is_valid(cache_entry)) {
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cache_entry.CacheState := state;
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}
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}
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AccessPermission getAccessPermission(Addr addr) {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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return TCC_State_to_permission(tbe.TBEState);
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}
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Entry cache_entry := getCacheEntry(addr);
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if(is_valid(cache_entry)) {
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return TCC_State_to_permission(cache_entry.CacheState);
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}
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return AccessPermission:NotPresent;
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}
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void setAccessPermission(Entry cache_entry, Addr addr, State state) {
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if (is_valid(cache_entry)) {
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cache_entry.changePermission(TCC_State_to_permission(state));
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}
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}
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void functionalRead(Addr addr, Packet *pkt) {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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testAndRead(addr, tbe.DataBlk, pkt);
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} else {
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functionalMemoryRead(pkt);
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}
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}
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int functionalWrite(Addr addr, Packet *pkt) {
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int num_functional_writes := 0;
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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num_functional_writes := num_functional_writes +
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testAndWrite(addr, tbe.DataBlk, pkt);
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}
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num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
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return num_functional_writes;
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}
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void recordRequestType(RequestType request_type, Addr addr) {
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if (request_type == RequestType:DataArrayRead) {
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L2cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
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} else if (request_type == RequestType:DataArrayWrite) {
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L2cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
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} else if (request_type == RequestType:TagArrayRead) {
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L2cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
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} else if (request_type == RequestType:TagArrayWrite) {
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L2cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
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}
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}
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bool checkResourceAvailable(RequestType request_type, Addr addr) {
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if (request_type == RequestType:DataArrayRead) {
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return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
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} else if (request_type == RequestType:DataArrayWrite) {
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return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
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} else if (request_type == RequestType:TagArrayRead) {
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return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
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} else if (request_type == RequestType:TagArrayWrite) {
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return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
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} else {
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error("Invalid RequestType type in checkResourceAvailable");
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return true;
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}
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}
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// OUT PORTS
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out_port(w_requestNetwork_out, CPURequestMsg, w_reqToTCCDir);
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out_port(w_TCCResp_out, ResponseMsg, w_respToTCCDir);
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out_port(responseNetwork_out, ResponseMsg, responseFromTCC);
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out_port(w_unblockNetwork_out, UnblockMsg, w_TCCUnblockToTCCDir);
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// IN PORTS
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in_port(TDResponse_in, ResponseMsg, w_respToTCC) {
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if (TDResponse_in.isReady(clockEdge())) {
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peek(TDResponse_in, ResponseMsg) {
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Entry cache_entry := getCacheEntry(in_msg.addr);
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TBE tbe := TBEs.lookup(in_msg.addr);
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if (in_msg.Type == CoherenceResponseType:TDSysWBAck) {
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trigger(Event:WBAck, in_msg.addr, cache_entry, tbe);
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}
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else {
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DPRINTF(RubySlicc, "%s\n", in_msg);
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error("Error on TDResponse Type");
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}
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}
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}
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}
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// Response Network
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in_port(responseNetwork_in, ResponseMsg, responseToTCC) {
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if (responseNetwork_in.isReady(clockEdge())) {
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peek(responseNetwork_in, ResponseMsg) {
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Entry cache_entry := getCacheEntry(in_msg.addr);
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TBE tbe := TBEs.lookup(in_msg.addr);
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if (in_msg.Type == CoherenceResponseType:CPUData) {
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if (in_msg.NbReqShared) {
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trigger(Event:CPUDataShared, in_msg.addr, cache_entry, tbe);
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} else {
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trigger(Event:CPUData, in_msg.addr, cache_entry, tbe);
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}
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} else if (in_msg.Type == CoherenceResponseType:StaleNotif) {
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trigger(Event:StaleWB, in_msg.addr, cache_entry, tbe);
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} else {
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DPRINTF(RubySlicc, "%s\n", in_msg);
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error("Error on TDResponse Type");
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}
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}
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}
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}
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// probe network
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in_port(probeNetwork_in, TDProbeRequestMsg, w_probeToTCC) {
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if (probeNetwork_in.isReady(clockEdge())) {
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peek(probeNetwork_in, TDProbeRequestMsg) {
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Entry cache_entry := getCacheEntry(in_msg.addr);
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TBE tbe := TBEs.lookup(in_msg.addr);
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if (in_msg.Type == ProbeRequestType:PrbInv) {
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if (in_msg.ReturnData) {
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trigger(Event:PrbInvData, in_msg.addr, cache_entry, tbe);
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} else {
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trigger(Event:PrbInv, in_msg.addr, cache_entry, tbe);
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}
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} else if (in_msg.Type == ProbeRequestType:PrbDowngrade) {
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if (in_msg.ReturnData) {
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trigger(Event:PrbShrData, in_msg.addr, cache_entry, tbe);
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} else {
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error("Don't think I should get any of these");
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}
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}
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}
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}
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}
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// Request Network
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in_port(requestNetwork_in, CPURequestMsg, w_reqToTCC) {
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if (requestNetwork_in.isReady(clockEdge())) {
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peek(requestNetwork_in, CPURequestMsg) {
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assert(in_msg.Destination.isElement(machineID));
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Entry cache_entry := getCacheEntry(in_msg.addr);
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TBE tbe := TBEs.lookup(in_msg.addr);
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if (in_msg.Type == CoherenceRequestType:RdBlk) {
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trigger(Event:RdBlk, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:RdBlkS) {
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trigger(Event:RdBlkS, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:RdBlkM) {
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trigger(Event:RdBlkM, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:VicClean) {
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if (presentOrAvail(in_msg.addr)) {
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if (in_msg.Shared) {
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trigger(Event:ClVicBlkShared, in_msg.addr, cache_entry, tbe);
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} else {
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trigger(Event:ClVicBlk, in_msg.addr, cache_entry, tbe);
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}
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} else {
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Addr victim := L2cache.cacheProbe(in_msg.addr);
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trigger(Event:L2_Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
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}
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} else if (in_msg.Type == CoherenceRequestType:VicDirty) {
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if (presentOrAvail(in_msg.addr)) {
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if (in_msg.Shared) {
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trigger(Event:WrVicBlkShared, in_msg.addr, cache_entry, tbe);
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} else {
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trigger(Event:WrVicBlk, in_msg.addr, cache_entry, tbe);
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}
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} else {
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Addr victim := L2cache.cacheProbe(in_msg.addr);
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trigger(Event:L2_Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
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}
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} else {
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requestNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
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}
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}
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}
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}
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// BEGIN ACTIONS
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action(i_invL2, "i", desc="invalidate TCC cache block") {
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if (is_valid(cache_entry)) {
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L2cache.deallocate(address);
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}
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unset_cache_entry();
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}
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action(rm_sendResponseM, "rm", desc="send Modified response") {
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peek(requestNetwork_in, CPURequestMsg) {
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enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:TDSysResp;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.DataBlk := cache_entry.DataBlk;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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out_msg.Dirty := cache_entry.Dirty;
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out_msg.State := CoherenceState:Modified;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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action(rs_sendResponseS, "rs", desc="send Shared response") {
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peek(requestNetwork_in, CPURequestMsg) {
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enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:TDSysResp;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.DataBlk := cache_entry.DataBlk;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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out_msg.Dirty := cache_entry.Dirty;
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out_msg.State := CoherenceState:Shared;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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action(r_requestToTD, "r", desc="Miss in L2, pass on") {
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peek(requestNetwork_in, CPURequestMsg) {
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enqueue(w_requestNetwork_out, CPURequestMsg, l2_request_latency) {
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out_msg.addr := address;
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out_msg.Type := in_msg.Type;
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out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.Shared := false; // unneeded for this request
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out_msg.MessageSize := in_msg.MessageSize;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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action(t_allocateTBE, "t", desc="allocate TBE Entry") {
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TBEs.allocate(address);
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set_tbe(TBEs.lookup(address));
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if (is_valid(cache_entry)) {
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tbe.DataBlk := cache_entry.DataBlk; // Data only for WBs
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tbe.Dirty := cache_entry.Dirty;
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}
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tbe.From := machineID;
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}
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action(dt_deallocateTBE, "dt", desc="deallocate TBE Entry") {
|
|
TBEs.deallocate(address);
|
|
unset_tbe();
|
|
}
|
|
|
|
action(vc_vicClean, "vc", desc="Victimize Clean L2 data") {
|
|
enqueue(w_requestNetwork_out, CPURequestMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceRequestType:VicClean;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
|
|
action(vd_vicDirty, "vd", desc="Victimize dirty L2 data") {
|
|
enqueue(w_requestNetwork_out, CPURequestMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceRequestType:VicDirty;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
|
|
action(w_sendResponseWBAck, "w", desc="send WB Ack") {
|
|
peek(requestNetwork_in, CPURequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceResponseType:TDSysWBAck;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.Sender := machineID;
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(pi_sendProbeResponseInv, "pi", desc="send probe ack inv, no data") {
|
|
enqueue(w_TCCResp_out, ResponseMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceResponseType:CPUPrbResp; // TCC and CPUs respond in same way to probes
|
|
out_msg.Sender := machineID;
|
|
// will this always be ok? probably not for multisocket
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.Dirty := false;
|
|
out_msg.Hit := false;
|
|
out_msg.Ntsl := true;
|
|
out_msg.State := CoherenceState:NA;
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
}
|
|
}
|
|
|
|
action(ph_sendProbeResponseHit, "ph", desc="send probe ack, no data") {
|
|
enqueue(w_TCCResp_out, ResponseMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceResponseType:CPUPrbResp; // TCC and CPUs respond in same way to probes
|
|
out_msg.Sender := machineID;
|
|
// will this always be ok? probably not for multisocket
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.Dirty := false;
|
|
out_msg.Hit := true;
|
|
out_msg.Ntsl := false;
|
|
out_msg.State := CoherenceState:NA;
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
}
|
|
}
|
|
|
|
action(pm_sendProbeResponseMiss, "pm", desc="send probe ack, no data") {
|
|
enqueue(w_TCCResp_out, ResponseMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceResponseType:CPUPrbResp; // TCC and CPUs respond in same way to probes
|
|
out_msg.Sender := machineID;
|
|
// will this always be ok? probably not for multisocket
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.Dirty := false;
|
|
out_msg.Hit := false;
|
|
out_msg.Ntsl := false;
|
|
out_msg.State := CoherenceState:NA;
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
}
|
|
}
|
|
|
|
action(pd_sendProbeResponseData, "pd", desc="send probe ack, with data") {
|
|
enqueue(w_TCCResp_out, ResponseMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceResponseType:CPUPrbResp; // TCC and CPUs respond in same way to probes
|
|
out_msg.Sender := machineID;
|
|
// will this always be ok? probably not for multisocket
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
//assert(cache_entry.Dirty); Not needed in TCC where TCC can supply clean data
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.Hit := true;
|
|
out_msg.State := CoherenceState:NA;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
|
|
action(pdt_sendProbeResponseDataFromTBE, "pdt", desc="send probe ack with data") {
|
|
enqueue(w_TCCResp_out, ResponseMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceResponseType:CPUPrbResp;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
//assert(tbe.Dirty);
|
|
out_msg.Dirty := tbe.Dirty;
|
|
out_msg.Hit := true;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.State := CoherenceState:NA;
|
|
DPRINTF(RubySlicc, "%s\n", out_msg);
|
|
}
|
|
}
|
|
|
|
action(mc_cancelMemWriteback, "mc", desc="send writeback cancel to memory") {
|
|
enqueue(w_requestNetwork_out, CPURequestMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceRequestType:WrCancel;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Request_Control;
|
|
}
|
|
}
|
|
|
|
action(a_allocateBlock, "a", desc="allocate TCC block") {
|
|
if (is_invalid(cache_entry)) {
|
|
set_cache_entry(L2cache.allocate(address, new Entry));
|
|
}
|
|
}
|
|
|
|
action(d_writeData, "d", desc="write data to TCC") {
|
|
peek(responseNetwork_in, ResponseMsg) {
|
|
if (in_msg.Dirty) {
|
|
cache_entry.Dirty := in_msg.Dirty;
|
|
}
|
|
cache_entry.DataBlk := in_msg.DataBlk;
|
|
DPRINTF(RubySlicc, "Writing to TCC: %s\n", in_msg);
|
|
}
|
|
}
|
|
|
|
action(rd_copyDataFromRequest, "rd", desc="write data to TCC") {
|
|
peek(requestNetwork_in, CPURequestMsg) {
|
|
cache_entry.DataBlk := in_msg.DataBlk;
|
|
cache_entry.Dirty := true;
|
|
}
|
|
}
|
|
|
|
action(f_setFrom, "f", desc="set who WB is expected to come from") {
|
|
peek(requestNetwork_in, CPURequestMsg) {
|
|
tbe.From := in_msg.Requestor;
|
|
}
|
|
}
|
|
|
|
action(rf_resetFrom, "rf", desc="reset From") {
|
|
tbe.From := machineID;
|
|
}
|
|
|
|
action(wb_data, "wb", desc="write back data") {
|
|
enqueue(w_TCCResp_out, ResponseMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceResponseType:CPUData;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
if (tbe.Shared) {
|
|
out_msg.NbReqShared := true;
|
|
} else {
|
|
out_msg.NbReqShared := false;
|
|
}
|
|
out_msg.State := CoherenceState:Shared; // faux info
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Data;
|
|
DPRINTF(RubySlicc, "%s\n", out_msg);
|
|
}
|
|
}
|
|
|
|
action(wt_writeDataToTBE, "wt", desc="write WB data to TBE") {
|
|
peek(responseNetwork_in, ResponseMsg) {
|
|
tbe.DataBlk := in_msg.DataBlk;
|
|
tbe.Dirty := in_msg.Dirty;
|
|
}
|
|
}
|
|
|
|
action(uo_sendUnblockOwner, "uo", desc="state changed to E, M, or O, unblock") {
|
|
enqueue(w_unblockNetwork_out, UnblockMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Unblock_Control;
|
|
out_msg.currentOwner := true;
|
|
out_msg.valid := true;
|
|
DPRINTF(RubySlicc, "%s\n", out_msg);
|
|
}
|
|
}
|
|
|
|
action(us_sendUnblockSharer, "us", desc="state changed to S , unblock") {
|
|
enqueue(w_unblockNetwork_out, UnblockMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Unblock_Control;
|
|
out_msg.currentOwner := false;
|
|
out_msg.valid := true;
|
|
DPRINTF(RubySlicc, "%s\n", out_msg);
|
|
}
|
|
}
|
|
|
|
action(un_sendUnblockNotValid, "un", desc="state changed toI, unblock") {
|
|
enqueue(w_unblockNetwork_out, UnblockMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Unblock_Control;
|
|
out_msg.currentOwner := false;
|
|
out_msg.valid := false;
|
|
DPRINTF(RubySlicc, "%s\n", out_msg);
|
|
}
|
|
}
|
|
|
|
action(ut_updateTag, "ut", desc="update Tag (i.e. set MRU)") {
|
|
L2cache.setMRU(address);
|
|
}
|
|
|
|
action(p_popRequestQueue, "p", desc="pop request queue") {
|
|
requestNetwork_in.dequeue(clockEdge());
|
|
}
|
|
|
|
action(pr_popResponseQueue, "pr", desc="pop response queue") {
|
|
responseNetwork_in.dequeue(clockEdge());
|
|
}
|
|
|
|
action(pn_popTDResponseQueue, "pn", desc="pop TD response queue") {
|
|
TDResponse_in.dequeue(clockEdge());
|
|
}
|
|
|
|
action(pp_popProbeQueue, "pp", desc="pop probe queue") {
|
|
probeNetwork_in.dequeue(clockEdge());
|
|
}
|
|
|
|
action(zz_recycleRequestQueue, "\z", desc="recycle request queue") {
|
|
requestNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
|
|
}
|
|
|
|
|
|
// END ACTIONS
|
|
|
|
// BEGIN TRANSITIONS
|
|
|
|
// transitions from base
|
|
|
|
transition({I, I_C}, {RdBlk, RdBlkS, RdBlkM, CtoD}){TagArrayRead} {
|
|
// TCCdir already knows that the block is not here. This is to allocate and get the block.
|
|
r_requestToTD;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// check
|
|
transition({M, O}, RdBlk, O){TagArrayRead, TagArrayWrite} {
|
|
rs_sendResponseS;
|
|
ut_updateTag;
|
|
// detect 2nd chancing
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
//check
|
|
transition({E, S}, RdBlk, S){TagArrayRead, TagArrayWrite} {
|
|
rs_sendResponseS;
|
|
ut_updateTag;
|
|
// detect 2nd chancing
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// check
|
|
transition({M, O}, RdBlkS, O){TagArrayRead, TagArrayWrite} {
|
|
rs_sendResponseS;
|
|
ut_updateTag;
|
|
// detect 2nd chance sharing
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
//check
|
|
transition({E, S}, RdBlkS, S){TagArrayRead, TagArrayWrite} {
|
|
rs_sendResponseS;
|
|
ut_updateTag;
|
|
// detect 2nd chance sharing
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// check
|
|
transition(M, RdBlkM, I){TagArrayRead, TagArrayWrite} {
|
|
rm_sendResponseM;
|
|
i_invL2;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
//check
|
|
transition(E, RdBlkM, I){TagArrayRead, TagArrayWrite} {
|
|
rm_sendResponseM;
|
|
i_invL2;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// check
|
|
transition({I}, WrVicBlk, I_M){TagArrayRead} {
|
|
a_allocateBlock;
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition(I_C, {WrVicBlk, WrVicBlkShared, ClVicBlk, ClVicBlkShared}) {
|
|
zz_recycleRequestQueue;
|
|
}
|
|
|
|
//check
|
|
transition({I}, WrVicBlkShared, I_O) {TagArrayRead}{
|
|
a_allocateBlock;
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
// rd_copyDataFromRequest;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
//check
|
|
transition(S, WrVicBlkShared, S_O){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(S, WrVicBlk, S_S){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(E, WrVicBlk, E_E){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(E, WrVicBlkShared, E_E){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(O, WrVicBlk, O_O){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(O, WrVicBlkShared, O_O){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(M, WrVicBlk, M_M){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(M, WrVicBlkShared, M_O){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
//check
|
|
transition({I}, ClVicBlk, I_E){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
a_allocateBlock;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition({I}, ClVicBlkShared, I_S){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
a_allocateBlock;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
//check
|
|
transition(S, ClVicBlkShared, S_S){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(E, ClVicBlk, E_E){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(E, ClVicBlkShared, E_S){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(O, ClVicBlk, O_O){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// check. Original L3 ahd it going from O to O_S. Something can go from O to S only on writeback.
|
|
transition(O, ClVicBlkShared, O_O){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(M, ClVicBlk, M_E){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
// a stale writeback
|
|
transition(M, ClVicBlkShared, M_S){TagArrayRead} {
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
|
|
transition({MO_I}, {RdBlk, RdBlkS, RdBlkM, CtoD}) {
|
|
a_allocateBlock;
|
|
t_allocateTBE;
|
|
f_setFrom;
|
|
r_requestToTD;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition(MO_I, {WrVicBlkShared, WrVicBlk, ClVicBlk, ClVicBlkShared}, MOD_I) {
|
|
f_setFrom;
|
|
w_sendResponseWBAck;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition(I_M, CPUData, M){TagArrayWrite} {
|
|
uo_sendUnblockOwner;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(I_M, CPUDataShared, O){TagArrayWrite, DataArrayWrite} {
|
|
uo_sendUnblockOwner;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(I_O, {CPUData, CPUDataShared}, O){TagArrayWrite, DataArrayWrite} {
|
|
uo_sendUnblockOwner;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(I_E, CPUData, E){TagArrayWrite, DataArrayWrite} {
|
|
uo_sendUnblockOwner;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(I_E, CPUDataShared, S){TagArrayWrite, DataArrayWrite} {
|
|
us_sendUnblockSharer;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(I_S, {CPUData, CPUDataShared}, S){TagArrayWrite, DataArrayWrite} {
|
|
us_sendUnblockSharer;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(S_M, CPUDataShared, O){TagArrayWrite, DataArrayWrite} {
|
|
uo_sendUnblockOwner;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
ut_updateTag; // update tag on writeback hits.
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(S_O, {CPUData, CPUDataShared}, O){TagArrayWrite, DataArrayWrite} {
|
|
uo_sendUnblockOwner;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
ut_updateTag; // update tag on writeback hits.
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(S_E, CPUDataShared, S){TagArrayWrite, DataArrayWrite} {
|
|
us_sendUnblockSharer;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
ut_updateTag; // update tag on writeback hits.
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(S_S, {CPUData, CPUDataShared}, S){TagArrayWrite, DataArrayWrite} {
|
|
us_sendUnblockSharer;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
ut_updateTag; // update tag on writeback hits.
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(O_E, CPUDataShared, O){TagArrayWrite, DataArrayWrite} {
|
|
uo_sendUnblockOwner;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
ut_updateTag; // update tag on writeback hits.
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(O_O, {CPUData, CPUDataShared}, O){TagArrayWrite, DataArrayWrite} {
|
|
uo_sendUnblockOwner;
|
|
dt_deallocateTBE;
|
|
d_writeData;
|
|
ut_updateTag; // update tag on writeback hits.
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition({D_I}, {CPUData, CPUDataShared}, I){TagArrayWrite} {
|
|
un_sendUnblockNotValid;
|
|
dt_deallocateTBE;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(MOD_I, {CPUData, CPUDataShared}, MO_I) {
|
|
un_sendUnblockNotValid;
|
|
rf_resetFrom;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition({O,S,I}, CPUData) {
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition({M, O}, L2_Repl, MO_I){TagArrayRead, DataArrayRead} {
|
|
t_allocateTBE;
|
|
vd_vicDirty;
|
|
i_invL2;
|
|
}
|
|
|
|
transition({E, S,}, L2_Repl, ES_I){TagArrayRead, DataArrayRead} {
|
|
t_allocateTBE;
|
|
vc_vicClean;
|
|
i_invL2;
|
|
}
|
|
|
|
transition({I_M, I_O, S_M, S_O, E_M, E_O}, L2_Repl) {
|
|
zz_recycleRequestQueue;
|
|
}
|
|
|
|
transition({O_M, O_O, O_E, M_M, M_O, M_E, M_S}, L2_Repl) {
|
|
zz_recycleRequestQueue;
|
|
}
|
|
|
|
transition({I_E, I_S, S_E, S_S, E_E, E_S}, L2_Repl) {
|
|
zz_recycleRequestQueue;
|
|
}
|
|
|
|
transition({M, O}, PrbInvData, I){TagArrayRead, TagArrayWrite} {
|
|
pd_sendProbeResponseData;
|
|
i_invL2;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(I, PrbInvData){TagArrayRead, TagArrayWrite} {
|
|
pi_sendProbeResponseInv;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition({E, S}, PrbInvData, I){TagArrayRead, TagArrayWrite} {
|
|
pd_sendProbeResponseData;
|
|
i_invL2;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition({M, O, E, S, I}, PrbInv, I){TagArrayRead, TagArrayWrite} {
|
|
pi_sendProbeResponseInv;
|
|
i_invL2; // nothing will happen in I
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition({M, O}, PrbShrData, O){TagArrayRead, TagArrayWrite} {
|
|
pd_sendProbeResponseData;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition({E, S}, PrbShrData, S){TagArrayRead, TagArrayWrite} {
|
|
pd_sendProbeResponseData;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(I, PrbShrData){TagArrayRead} {
|
|
pm_sendProbeResponseMiss;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(MO_I, PrbInvData, I_C) {
|
|
pdt_sendProbeResponseDataFromTBE;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(ES_I, PrbInvData, I_C) {
|
|
pi_sendProbeResponseInv;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition({ES_I,MO_I}, PrbInv, I_C) {
|
|
pi_sendProbeResponseInv;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition({ES_I, MO_I}, PrbShrData) {
|
|
pdt_sendProbeResponseDataFromTBE;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(I_C, {PrbInvData, PrbInv}) {
|
|
pi_sendProbeResponseInv;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(I_C, PrbShrData) {
|
|
pm_sendProbeResponseMiss;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(MOD_I, WBAck, D_I) {
|
|
pn_popTDResponseQueue;
|
|
}
|
|
|
|
transition(MO_I, WBAck, I){TagArrayWrite} {
|
|
dt_deallocateTBE;
|
|
pn_popTDResponseQueue;
|
|
}
|
|
|
|
// this can only be a spurious CPUData from a shared block.
|
|
transition(MO_I, CPUData) {
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(ES_I, WBAck, I){TagArrayWrite} {
|
|
dt_deallocateTBE;
|
|
pn_popTDResponseQueue;
|
|
}
|
|
|
|
transition(I_C, {WBAck}, I){TagArrayWrite} {
|
|
dt_deallocateTBE;
|
|
pn_popTDResponseQueue;
|
|
}
|
|
|
|
transition({I_M, I_O, I_E, I_S}, StaleWB, I){TagArrayWrite} {
|
|
un_sendUnblockNotValid;
|
|
dt_deallocateTBE;
|
|
i_invL2;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition({S_S, S_O, S_M, S_E}, StaleWB, S){TagArrayWrite} {
|
|
us_sendUnblockSharer;
|
|
dt_deallocateTBE;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition({E_M, E_O, E_E, E_S}, StaleWB, E){TagArrayWrite} {
|
|
uo_sendUnblockOwner;
|
|
dt_deallocateTBE;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition({O_M, O_O, O_E}, StaleWB, O){TagArrayWrite} {
|
|
uo_sendUnblockOwner;
|
|
dt_deallocateTBE;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition({M_M, M_O, M_E, M_S}, StaleWB, M){TagArrayWrite} {
|
|
uo_sendUnblockOwner;
|
|
dt_deallocateTBE;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(D_I, StaleWB, I) {TagArrayWrite}{
|
|
un_sendUnblockNotValid;
|
|
dt_deallocateTBE;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(MOD_I, StaleWB, MO_I) {
|
|
un_sendUnblockNotValid;
|
|
rf_resetFrom;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
}
|