c120273708
The directed tester supports only generating only read or only write accesses. The patch modifies the tester to support streams that have both read and write accesses.
59 lines
2.8 KiB
Python
59 lines
2.8 KiB
Python
# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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from m5.SimObject import SimObject
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from MemObject import MemObject
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from m5.params import *
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from m5.proxy import *
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class DirectedGenerator(SimObject):
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type = 'DirectedGenerator'
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abstract = True
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cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh"
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num_cpus = Param.Int("num of cpus")
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system = Param.System(Parent.any, "System we belong to")
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class SeriesRequestGenerator(DirectedGenerator):
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type = 'SeriesRequestGenerator'
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cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh"
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addr_increment_size = Param.Int(64, "address increment size")
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num_series = Param.UInt32(1,
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"number of different address streams to generate")
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percent_writes = Param.Percent(50, "percent of access that are writes")
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class InvalidateGenerator(DirectedGenerator):
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type = 'InvalidateGenerator'
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cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh"
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addr_increment_size = Param.Int(64, "address increment size")
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class RubyDirectedTester(MemObject):
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type = 'RubyDirectedTester'
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cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh"
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cpuPort = VectorMasterPort("the cpu ports")
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requests_to_complete = Param.Int("checks to complete")
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generator = Param.DirectedGenerator("the request generator")
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