Andreas Sandberg 326662b01b arch, cpu: Factor out the ExecContext into a proper base class ... We currently generate and compile one version of the ISA code per CPU model. This is obviously wasting a lot of resources at compile time. This changeset factors out the interface into a separate ExecContext class, which also serves as documentation for the interface between CPUs and the ISA code. While doing so, this changeset also fixes up interface inconsistencies between the different CPU models. The main argument for using one set of ISA code per CPU model has always been performance as this avoid indirect branches in the generated code. However, this argument does not hold water. Booting Linux on a simulated ARM system running in atomic mode (opt/10.linux-boot/realview-simple-atomic) is actually 2% faster (compiled using clang 3.4) after applying this patch. Additionally, compilation time is decreased by 35%.		2014-09-03 07:42:22 -04:00
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alpha	arch: Cleanup unused ISA traits constants	2014-09-03 07:42:21 -04:00
arm	arch, cpu: Factor out the ExecContext into a proper base class	2014-09-03 07:42:22 -04:00
generic	base: Replace the internal varargs stuff with C++11 constructs	2014-08-26 10:13:45 -04:00
mips	arch: Cleanup unused ISA traits constants	2014-09-03 07:42:21 -04:00
null	arch: Cleanup unused ISA traits constants	2014-09-03 07:42:21 -04:00
power	arch: Cleanup unused ISA traits constants	2014-09-03 07:42:21 -04:00
sparc	arch: Cleanup unused ISA traits constants	2014-09-03 07:42:21 -04:00
x86	arch: Cleanup unused ISA traits constants	2014-09-03 07:42:21 -04:00
isa_parser.py	arch, cpu: Factor out the ExecContext into a proper base class	2014-09-03 07:42:22 -04:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	arch, cpu: Factor out the ExecContext into a proper base class	2014-09-03 07:42:22 -04:00