448 lines
48 KiB
Text
448 lines
48 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 36236154 # Number of BTB hits
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global.BPredUnit.BTBLookups 45185962 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 1073 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 5716683 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 34971489 # Number of conditional branches predicted
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global.BPredUnit.lookups 61628084 # Number of BP lookups
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global.BPredUnit.usedRAS 12361715 # Number of times the RAS was used to get a target.
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host_inst_rate 99282 # Simulator instruction rate (inst/s)
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host_mem_usage 157844 # Number of bytes of host memory used
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host_seconds 3782.92 # Real time elapsed on the host
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host_tick_rate 35167352 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 72386416 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 49504127 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 123653839 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 91343872 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 375574833 # Number of instructions simulated
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sim_seconds 0.133035 # Number of seconds simulated
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sim_ticks 133035205000 # Number of ticks simulated
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system.cpu.commit.COM:branches 44587535 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 13438686 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 251297305
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 121146881 4820.86%
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1 48729398 1939.11%
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2 18716292 744.79%
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3 21031196 836.90%
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4 10746871 427.66%
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5 8854080 352.33%
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6 5795641 230.63%
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7 2838260 112.94%
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8 13438686 534.77%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 398664608 # Number of instructions committed
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system.cpu.commit.COM:loads 100651996 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 174183399 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 5712494 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 398664608 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 90429807 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 375574833 # Number of Instructions Simulated
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system.cpu.committedInsts_total 375574833 # Number of Instructions Simulated
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system.cpu.cpi 0.708435 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.708435 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 94590513 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 11093.306288 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5614.604462 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 94589527 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 10938000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 986 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 502 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 5536000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 73513283 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 23569.486405 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6046.374622 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 73509973 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 78015000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 7447 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 20013500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 40244.103424 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 168103796 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 20706.005587 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 5947.276536 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 168099500 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 88953000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000026 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 4296 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 7949 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 25549500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 4296 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 168103796 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 20706.005587 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 5947.276536 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 168099500 # number of overall hits
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system.cpu.dcache.overall_miss_latency 88953000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000026 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 4296 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 7949 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 25549500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 4296 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 781 # number of replacements
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system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 3296.752220 # Cycle average of tags in use
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system.cpu.dcache.total_refs 168099620 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 636 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 18878594 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 4321 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 11282111 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 527703627 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 131753678 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 99378321 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 14771982 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 12721 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 1286713 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 182322311 # DTB accesses
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system.cpu.dtb.acv 11231 # DTB access violations
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system.cpu.dtb.hits 182284581 # DTB hits
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system.cpu.dtb.misses 37730 # DTB misses
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system.cpu.dtb.read_accesses 103122587 # DTB read accesses
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system.cpu.dtb.read_acv 11230 # DTB read access violations
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system.cpu.dtb.read_hits 103086401 # DTB read hits
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system.cpu.dtb.read_misses 36186 # DTB read misses
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system.cpu.dtb.write_accesses 79199724 # DTB write accesses
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system.cpu.dtb.write_acv 1 # DTB write access violations
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system.cpu.dtb.write_hits 79198180 # DTB write hits
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system.cpu.dtb.write_misses 1544 # DTB write misses
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system.cpu.fetch.Branches 61628084 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 63320961 # Number of cache lines fetched
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system.cpu.fetch.Cycles 166618115 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 1484455 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 541175943 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 6060115 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.231623 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 63320961 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 48597869 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 2.033958 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 266069288
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system.cpu.fetch.rateDist.min_value 0
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0 162772436 6117.67%
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1 10792214 405.62%
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2 11562978 434.59%
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3 6945740 261.05%
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4 14845221 557.95%
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5 9644746 362.49%
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6 6640124 249.56%
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7 3951437 148.51%
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8 38914392 1462.57%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 63320771 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 7179.953858 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 4985.644706 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 63316870 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 28009000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 3901 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 190 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 19449000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000062 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 3901 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 16230.933094 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 63320771 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 7179.953858 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 4985.644706 # average overall mshr miss latency
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system.cpu.icache.demand_hits 63316870 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 28009000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses
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system.cpu.icache.demand_misses 3901 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 190 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 19449000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000062 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 3901 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 63320771 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 7179.953858 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 4985.644706 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 63316870 # number of overall hits
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system.cpu.icache.overall_miss_latency 28009000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses
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system.cpu.icache.overall_misses 3901 # number of overall misses
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system.cpu.icache.overall_mshr_hits 190 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 19449000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000062 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 3901 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 1979 # number of replacements
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system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1826.105929 # Cycle average of tags in use
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system.cpu.icache.total_refs 63316870 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 1124 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 50342697 # Number of branches executed
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system.cpu.iew.EXEC:nop 27143660 # number of nop insts executed
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system.cpu.iew.EXEC:rate 1.556730 # Inst execution rate
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system.cpu.iew.EXEC:refs 189044982 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 79210411 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 284353015 # num instructions consuming a value
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system.cpu.iew.WB:count 410949767 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.699040 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 198774253 # num instructions producing a value
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system.cpu.iew.WB:rate 1.544515 # insts written-back per cycle
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system.cpu.iew.WB:sent 411560855 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 6153520 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 2291780 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 123653839 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 6328938 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 91343872 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 489095367 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 109834571 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 9454650 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 414199709 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 219457 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 24015 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 14771982 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 586141 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 8319023 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 12177 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 423678 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 176362 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 23001843 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 17812469 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 423678 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 800835 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 5352685 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 1.411562 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.411562 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 423654359 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 33581 0.01% # Type of FU issued
|
|
IntAlu 164699955 38.88% # Type of FU issued
|
|
IntMult 2150553 0.51% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 34423933 8.13% # Type of FU issued
|
|
FloatCmp 7590989 1.79% # Type of FU issued
|
|
FloatCvt 2918170 0.69% # Type of FU issued
|
|
FloatMult 16813198 3.97% # Type of FU issued
|
|
FloatDiv 1589024 0.38% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 112375969 26.53% # Type of FU issued
|
|
MemWrite 81058987 19.13% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 9621593 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.022711 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 40277 0.42% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 97634 1.01% # attempts to use FU when none available
|
|
FloatCmp 3955 0.04% # attempts to use FU when none available
|
|
FloatCvt 14420 0.15% # attempts to use FU when none available
|
|
FloatMult 1625332 16.89% # attempts to use FU when none available
|
|
FloatDiv 750896 7.80% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 5547187 57.65% # attempts to use FU when none available
|
|
MemWrite 1541892 16.03% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 266069288
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 96503300 3627.00%
|
|
1 57159929 2148.31%
|
|
2 40537288 1523.56%
|
|
3 30901170 1161.40%
|
|
4 22699747 853.15%
|
|
5 10809299 406.26%
|
|
6 4873798 183.18%
|
|
7 2049983 77.05%
|
|
8 534774 20.10%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 1.592264 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 461951468 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 423654359 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 85357325 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 903613 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 69252259 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 63321261 # ITB accesses
|
|
system.cpu.itb.acv 2 # ITB acv
|
|
system.cpu.itb.hits 63320961 # ITB hits
|
|
system.cpu.itb.misses 300 # ITB misses
|
|
system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 4638.497653 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2638.497653 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 14820000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 3195 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 8430000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 3195 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 4883 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4341.521020 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2341.521020 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 649 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 18382000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.867090 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 4234 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 9914000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.867090 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 4234 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 121 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4500 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2500 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 544500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 121 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 302500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 121 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 636 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 636 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.128626 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 8078 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 4469.242159 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2469.242159 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 649 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 33202000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.919658 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 7429 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 18344000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.919658 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 7429 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 8078 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 4469.242159 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2469.242159 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 649 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 33202000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.919658 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 7429 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 18344000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.919658 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 7429 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 15 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 4688 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 3886.512098 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 603 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.numCycles 266070412 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 9037497 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 259532351 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 1658142 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 136681474 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 7036650 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 676869332 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 514036809 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 332594976 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 95406326 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 14771982 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 9818184 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 73062625 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 353825 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 37914 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 21299684 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 252 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 417 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|