438 lines
47 KiB
Text
438 lines
47 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 185907621 # Number of BTB hits
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global.BPredUnit.BTBLookups 211172077 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 84388329 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 259737867 # Number of conditional branches predicted
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global.BPredUnit.lookups 259737867 # Number of BP lookups
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global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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host_inst_rate 60132 # Simulator instruction rate (inst/s)
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host_mem_usage 181784 # Number of bytes of host memory used
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host_seconds 23375.38 # Real time elapsed on the host
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host_tick_rate 47481565 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 469164607 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 147914514 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 750060478 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 305538857 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1405610551 # Number of instructions simulated
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sim_seconds 1.109900 # Number of seconds simulated
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sim_ticks 1109899556500 # Number of ticks simulated
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system.cpu.commit.COM:branches 86246390 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 8131436 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 1976139127
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 1095749998 5544.90%
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1 581465878 2942.43%
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2 120709498 610.84%
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3 119935544 606.92%
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4 28050272 141.94%
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5 7339488 37.14%
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6 10411639 52.69%
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7 4345374 21.99%
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8 8131436 41.15%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 1489528974 # Number of instructions committed
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system.cpu.commit.COM:loads 402516087 # Number of loads committed
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system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
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system.cpu.commit.COM:refs 569373869 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 84388329 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1489528974 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 1415029138 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1405610551 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1405610551 # Number of Instructions Simulated
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system.cpu.cpi 1.579242 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.579242 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 423053343 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 15772.083502 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2729.132935 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 422816175 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 3740633500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000561 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 237168 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 599122 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 647263000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000561 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 237168 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_avg_miss_latency 7087.500000 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5087.500000 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
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system.cpu.dcache.SwapReq_miss_latency 283500 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
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system.cpu.dcache.SwapReq_mshr_miss_latency 203500 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 165053818 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 45542.600793 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5916.879810 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 164707416 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 15776048000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.002099 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 346402 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1802638 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2049619000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.002099 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 346402 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 1146.620565 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 588107161 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 33443.599740 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 4621.351337 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 587523591 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 19516681500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000992 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 583570 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2401760 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 2696882000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000992 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 583570 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 588107161 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 33443.599740 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 4621.351337 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 587523591 # number of overall hits
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system.cpu.dcache.overall_miss_latency 19516681500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000992 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 583570 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2401760 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 2696882000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000992 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 583570 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 508363 # number of replacements
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system.cpu.dcache.sampled_refs 512459 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.764839 # Cycle average of tags in use
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system.cpu.dcache.total_refs 587596028 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 80528000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 343236 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 411423589 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:DecodedInsts 3483733335 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 768911971 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 792962132 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 243659831 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:UnblockCycles 2841435 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 259737867 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 358807696 # Number of cache lines fetched
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system.cpu.fetch.Cycles 1213889868 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 12053122 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 3775936768 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 90315783 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.117010 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 358807696 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 185907621 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.701026 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 2219798958
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system.cpu.fetch.rateDist.min_value 0
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0 1364716830 6147.93%
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1 258967518 1166.63%
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2 83143428 374.55%
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3 38353275 172.78%
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4 87812104 395.59%
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5 41187584 185.55%
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6 32935987 148.37%
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7 20637545 92.97%
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8 292044687 1315.64%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 358807628 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 7480.059084 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 5308.714919 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 358806274 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 10128000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 1354 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 7188000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 1354 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 264997.248154 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 358807628 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 7480.059084 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 5308.714919 # average overall mshr miss latency
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system.cpu.icache.demand_hits 358806274 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 10128000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
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system.cpu.icache.demand_misses 1354 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 68 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 7188000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 1354 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 358807628 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 7480.059084 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 5308.714919 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 358806274 # number of overall hits
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system.cpu.icache.overall_miss_latency 10128000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
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system.cpu.icache.overall_misses 1354 # number of overall misses
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system.cpu.icache.overall_mshr_hits 68 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 7188000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 1354 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 206 # number of replacements
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system.cpu.icache.sampled_refs 1354 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1043.219654 # Cycle average of tags in use
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system.cpu.icache.total_refs 358806274 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 156 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 127603528 # Number of branches executed
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system.cpu.iew.EXEC:nop 356521630 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.852457 # Inst execution rate
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system.cpu.iew.EXEC:refs 746062439 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 207373942 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 1493031889 # num instructions consuming a value
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system.cpu.iew.WB:count 1859658958 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.962656 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 1437276141 # num instructions producing a value
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system.cpu.iew.WB:rate 0.837760 # insts written-back per cycle
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system.cpu.iew.WB:sent 1869182188 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 90142069 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 426198 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 750060478 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 21374388 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 17119395 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 305538857 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 2904603510 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 538688497 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 102140333 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 1892283108 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 19664 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 4147 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 243659831 # Number of cycles IEW is squashing
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system.cpu.iew.iewUnblockCycles 32077 # Number of cycles IEW is unblocking
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 115016780 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 46174 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 6167113 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 30 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 347544391 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 138681075 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 6167113 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 1511945 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 88630124 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.633215 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.633215 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 1994423441 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 0 0.00% # Type of FU issued
|
|
IntAlu 1187879871 59.56% # Type of FU issued
|
|
IntMult 0 0.00% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 2994707 0.15% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 575372220 28.85% # Type of FU issued
|
|
MemWrite 228176643 11.44% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 4059109 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.002035 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 143359 3.53% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 223654 5.51% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 3316143 81.70% # attempts to use FU when none available
|
|
MemWrite 375953 9.26% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 2219798958
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 1092127511 4919.94%
|
|
1 592160180 2667.63%
|
|
2 301053468 1356.22%
|
|
3 164170369 739.57%
|
|
4 50664484 228.24%
|
|
5 13356785 60.17%
|
|
6 5787626 26.07%
|
|
7 350679 1.58%
|
|
8 127856 0.58%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 0.898470 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 2526420335 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 1994423441 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 21661545 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 1099219582 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 637228 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 19418044 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 1350410508 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.l2cache.ReadExReq_accesses 275291 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 4810.268044 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2810.268044 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1324223500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 275291 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 773641500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 275291 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 238522 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4132.403832 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2132.403832 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 203557 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 144489500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.146590 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 34965 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 74559500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146590 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 34965 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 71158 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4269.526968 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2269.653447 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 303811000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 71158 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 161504000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 71158 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 343236 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 343236 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 4.069566 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 513813 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 4733.874607 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2733.874607 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 203557 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 1468713000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.603831 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 310256 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 848201000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.603831 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 310256 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 513813 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 4733.874607 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2733.874607 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 203557 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 1468713000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.603831 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 310256 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 848201000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.603831 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 310256 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 84454 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 99919 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 16408.026694 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 406627 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 61955 # number of writebacks
|
|
system.cpu.numCycles 2219799114 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 14139757 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 1244771059 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:FullRegisterEvents 11 # Number of times there has been no free registers
|
|
system.cpu.rename.RENAME:IQFullEvents 15246 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 833407854 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 22992244 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 4967044310 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 3128619871 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 2442811426 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 727931337 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 243659831 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 32162189 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 1198040367 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 368497990 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 22007928 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 169677376 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 21764302 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 35 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|