d7fba9784e
Most of the changes were to fix broken macros in platfrom_tlaser.s
palcode/Makefile:
Completly new makefile to build palcode
palcode/ev5_alpha_defs.h:
fixed a broken define
palcode/ev5_impure.h:
macro fixes
palcode/platform_srcmax.s:
manual macro expansion of broken macros... this file isn't needed to
build tlaser palcode
palcode/platform_tlaser.s:
lots of fixups to make the code assemble
171 lines
4.7 KiB
C
171 lines
4.7 KiB
C
/* $Id: tlaserreg.h,v 1.3 2002/10/27 14:28:17 binkertn Exp $ */
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/*
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* Copyright (C) 1998 by the Board of Trustees
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* of Leland Stanford Junior University.
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* Copyright (C) 1998 Digital Equipment Corporation
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*
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* This file is part of the SimOS distribution.
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* See LICENSE file for terms of the license.
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*
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*/
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#ifndef __TLASERREG_H__
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#define __TLASERREG_H__
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///////////////////////////////////////////////////////////////////////
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//
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// This file is also included to build the palcode
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//
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// Common module defines
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#define TLDEV_REG 0x00
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#define TLBER_REG 0x40
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#define TLCNR_REG 0x80
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#define TLFADR0_REG 0x600
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#define TLFADR1_REG 0x640
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#define TLESR0_REG 0x680
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#define TLESR1_REG 0x6c0
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#define TLESR2_REG 0x700
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#define TLESR3_REG 0x740
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// I/O Module defines
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#define TLMMR0_REG 0x200
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#define TLMMR1_REG 0x240
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#define TLMMR2_REG 0x280
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#define TLMMR3_REG 0x2c0
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#define TLMMR4_REG 0x300
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#define TLMMR5_REG 0x340
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#define TLMMR6_REG 0x380
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#define TLMMR7_REG 0x3c0
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#define TLCPUMASK_REG 0x0b00
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#define TLILID0_REG 0xa00
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#define TLILID1_REG 0xa40
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#define TLILID2_REG 0xa80
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#define TLILID3_REG 0xac0
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#define TLMBPR_REG 0xc00
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#define ICCMSR_REG 0x2000
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#define ICCMTR_REG 0x20c0
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#define ICCWTR_REG 0x2100
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#define ICCNSE_REG 0x2040
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#define IDPNSE0_REG 0x2a40
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#define IDPNSE1_REG 0x2140
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#define IDPNSE2_REG 0x2240
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#define IDPNSE3_REG 0x2340
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#define IDPVR_REG 0x2b40
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#define IDPDR0_REG 0x2a80
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#define IDPDR1_REG 0x2180
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#define IDPDR2_REG 0x2280
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#define IDPDR3_REG 0x2380
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// CPU Module defines
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#define CPU0_OFFSET 0x0000
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#define CPU1_OFFSET 0x0040
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#define TLVID_REG 0x00c0
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#define TLDIAG_REG 0x1000
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#define TLMODCONFIG_REG 0x10c0
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#define TLINTRMASK0_REG 0x1100
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#define TLINTRMASK1_REG 0x1140
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#define TLINTRSUM0_REG 0x1180
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#define TLINTRSUM1_REG 0x11c0
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#define TLEPAERR_REG 0x1500
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#define TLEPDERR_REG 0x1540
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#define TLEPMERR_REG 0x1580
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#define TLEP_VMG_REG 0x15c0
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#define TLEPWERR_REG 0x1600
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// Memory Module defines
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#define MCR_REG 0x1880
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#define MIR_REG 0x1840
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#define MDRA_REG 0x1980
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#define MER_REG 0x1940
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#define DDR0_REG 0x10140
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#define DDR1_REG 0x14140
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#define DDR2_REG 0x18140
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#define DDR3_REG 0x1c140
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// Broadcast defines
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#define BROADCAST_NODE 0x18
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#define TLIPINTR_REG 0x40
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// GBUS defines
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#define GBUS_BASE ULL(0xfffffcff90000000)
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#define GBUS_BIT_SHIFT 0x06
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#define FLASH_BASE 0x07000000
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#define UART_BASE 0x10000000
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#define WATCH_CSR_BASE 0x20000000
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#define WHATAMI_REG 0x30000000
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#define MISCR_REG 0x34000000
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#define SERNUM_REG 0x37000000
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// RTC defines
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#define RTC_SECOND 0 // second of minute [0..59]
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#define RTC_SECOND_ALARM 1 // seconds to alarm
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#define RTC_MINUTE 2 // minute of hour [0..59]
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#define RTC_MINUTE_ALARM 3 // minutes to alarm
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#define RTC_HOUR 4 // hour of day [0..23]
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#define RTC_HOUR_ALARM 5 // hours to alarm
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#define RTC_DAY_OF_WEEK 6 // day of week [1..7]
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#define RTC_DAY_OF_MONTH 7 // day of month [1..31]
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#define RTC_MONTH 8 // month of year [1..12]
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#define RTC_YEAR 9 // year [00..99]
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#define RTC_CONTROL_REGISTERA 10 // control register A
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#define RTC_CONTROL_REGISTERB 11 // control register B
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#define RTC_CONTROL_REGISTERC 12 // control register C
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#define RTC_CONTROL_REGISTERD 13 // control register D
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#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1
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// Other defines
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#define DEVICE_TYPE_TIOP 0x2000
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#define DEVICE_TYPE_MEM 0x4000
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#define DEVICE_TYPE_CPU 0x8000
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///////////////////////////////////////////////////////////////////////
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//
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// litterals used in the platform_tlaser.s file.
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//
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// -DBUILD_PALCODE is only defined then. The compilation does include
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// this file from the simulation source tree.
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//
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// It is NOT an obsolete compilation option
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//
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#ifdef BUILD_PALCODE
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#define tlep_lintrsum0_offset 0x1180
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#define tlep_lintrsum1_offset 0x11c0
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#define tlep_tlintrsum0_offset tlep_lintrsum0_offset
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#define tlep_tlintrsum1_offset tlep_lintrsum1_offset
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#define tlep_watch_csrc_offset (RTC_CONTROL_REGISTERC <<GBUS_BIT_SHIFT)
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#define tlsb_tlber TLBER_REG
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#define tlsb_tlber_offset tlsb_tlber /* ??? */
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#define tlsb_tldev TLDEV_REG
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#define tlsb_tlesr0 TLESR0_REG
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#define tlsb_tlesr1 TLESR1_REG
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#define tlsb_tlesr2 TLESR2_REG
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#define tlsb_tlesr3 TLESR3_REG
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#define tlsb_tlilid0_offset TLILID0_REG
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#define tlsb_tlilid1_offset TLILID1_REG
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#define tlsb_tlilid2_offset TLILID2_REG
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#define tlsb_tlilid3_offset TLILID3_REG
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#define TLSB_TLIPINTR_OFFSET TLIPINTR_REG
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#endif // BUILD_PALCODE
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///////////////////////////////////////////////////////////////////////
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//
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// Codes used to probe/clear the TLINTRSUM register
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//
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#define TLASER_INTRSUM_UART 1 // uart
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#define TLASER_INTRSUM_IPI 0x20 // IPI
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#define TLASER_INTRSUM_INTIM 0x40 // clock
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#endif // __TLASERREG_H__
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