139 lines
4.4 KiB
C++
139 lines
4.4 KiB
C++
/* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_INSTS_BRANCH_HH__
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#define __ARCH_ARM_INSTS_BRANCH_HH__
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#include "arch/arm/insts/pred_inst.hh"
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namespace ArmISA
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{
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/**
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* Base class for instructions whose disassembly is not purely a
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* function of the machine instruction (i.e., it depends on the
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* PC). This class overrides the disassemble() method to check
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* the PC and symbol table values before re-using a cached
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* disassembly string. This is necessary for branches and jumps,
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* where the disassembly string includes the target address (which
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* may depend on the PC and/or symbol table).
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*/
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class PCDependentDisassembly : public PredOp
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{
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protected:
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/// Cached program counter from last disassembly
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mutable Addr cachedPC;
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/// Cached symbol table pointer from last disassembly
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mutable const SymbolTable *cachedSymtab;
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/// Constructor
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PCDependentDisassembly(const char *mnem, MachInst _machInst,
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OpClass __opClass)
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: PredOp(mnem, _machInst, __opClass),
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cachedPC(0), cachedSymtab(0)
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{
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}
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const std::string &
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disassemble(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for branches (PC-relative control transfers),
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* conditional or unconditional.
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*/
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class Branch : public PCDependentDisassembly
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{
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protected:
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/// target address (signed) Displacement .
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int32_t disp;
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/// Constructor.
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Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(machInst.offset << 2)
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{
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//If Bit 26 is 1 then Sign Extend
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if ( (disp & 0x02000000) > 0 ) {
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disp |= 0xFC000000;
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}
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}
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Addr branchTarget(Addr branchPC) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for branch and exchange instructions on the ARM
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*/
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class BranchExchange : public PredOp
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{
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protected:
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/// Constructor
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BranchExchange(const char *mnem, MachInst _machInst,
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OpClass __opClass)
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: PredOp(mnem, _machInst, __opClass)
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{
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for jumps (register-indirect control transfers). In
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* the Arm ISA, these are always unconditional.
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*/
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class Jump : public PCDependentDisassembly
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{
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protected:
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/// Displacement to target address (signed).
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int32_t disp;
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uint32_t target;
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public:
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/// Constructor
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Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(machInst.offset << 2)
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{
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}
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Addr branchTarget(ThreadContext *tc) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}
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#endif //__ARCH_ARM_INSTS_BRANCH_HH__
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