0deef376d9
This patch includes software engineering changes and some generic bug fixes
Joel Hestness and Yasuko Eckert made to McPAT 0.8. There are still known
issues/concernts we did not have a chance to address in this patch.
High-level changes in this patch include:
1) Making XML parsing modular and hierarchical:
- Shift parsing responsibility into the components
- Read XML in a (mostly) context-free recursive manner so that McPAT input
files can contain arbitrary component hierarchies
2) Making power, energy, and area calculations a hierarchical and recursive
process
- Components track their subcomponents and recursively call compute
functions in stages
- Make C++ object hierarchy reflect inheritance of classes of components
with similar structures
- Simplify computeArea() and computeEnergy() functions to eliminate
successive calls to calculate separate TDP vs. runtime energy
- Remove Processor component (now unnecessary) and introduce a more abstract
System component
3) Standardizing McPAT output across all components
- Use a single, common data structure for storing and printing McPAT output
- Recursively call print functions through component hierarchy
4) For caches, allow splitting data array and tag array reads and writes for
better accuracy
5) Improving the usability of CACTI by printing more helpful warning and error
messages
6) Minor: Impose more rigorous code style for clarity (more work still to be
done)
Overall, these changes greatly reduce the amount of replicated code, and they
improve McPAT runtime and decrease memory footprint.
546 lines
17 KiB
C++
546 lines
17 KiB
C++
/*****************************************************************************
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* McPAT/CACTI
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2012 Hewlett-Packard Development Company, L.P.
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* Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#ifndef __CACTI_INTERFACE_H__
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#define __CACTI_INTERFACE_H__
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#include <iostream>
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#include <list>
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#include <map>
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#include <string>
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#include <vector>
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#include "const.h"
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using namespace std;
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class min_values_t;
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class mem_array;
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class uca_org_t;
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class powerComponents {
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public:
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double dynamic;
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double leakage;
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double gate_leakage;
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double short_circuit;
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double longer_channel_leakage;
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powerComponents() : dynamic(0), leakage(0), gate_leakage(0), short_circuit(0), longer_channel_leakage(0) { }
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powerComponents(const powerComponents & obj) {
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*this = obj;
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}
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powerComponents & operator=(const powerComponents & rhs) {
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dynamic = rhs.dynamic;
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leakage = rhs.leakage;
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gate_leakage = rhs.gate_leakage;
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short_circuit = rhs.short_circuit;
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longer_channel_leakage = rhs.longer_channel_leakage;
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return *this;
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}
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void reset() {
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dynamic = 0;
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leakage = 0;
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gate_leakage = 0;
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short_circuit = 0;
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longer_channel_leakage = 0;
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}
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friend powerComponents operator+(const powerComponents & x, const powerComponents & y);
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friend powerComponents operator*(const powerComponents & x, double const * const y);
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};
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class powerDef {
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public:
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powerComponents readOp;
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powerComponents writeOp;
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powerComponents searchOp;//Sheng: for CAM and FA
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powerDef() : readOp(), writeOp(), searchOp() { }
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void reset() {
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readOp.reset();
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writeOp.reset();
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searchOp.reset();
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}
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friend powerDef operator+(const powerDef & x, const powerDef & y);
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friend powerDef operator*(const powerDef & x, double const * const y);
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};
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enum Wire_type {
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Global /* gloabl wires with repeaters */,
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Global_5 /* 5% delay penalty */,
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Global_10 /* 10% delay penalty */,
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Global_20 /* 20% delay penalty */,
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Global_30 /* 30% delay penalty */,
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Low_swing /* differential low power wires with high area overhead */,
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Semi_global /* mid-level wires with repeaters*/,
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Transmission /* tranmission lines with high area overhead */,
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Optical /* optical wires */,
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Invalid_wtype
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};
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class InputParameter {
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public:
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void parse_cfg(const string & infile);
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// return false if the input parameters are problematic
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bool error_checking(string name = "CACTI");
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void display_ip();
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unsigned int cache_sz; // in bytes
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unsigned int line_sz;
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unsigned int assoc;
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unsigned int nbanks;
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unsigned int out_w;// == nr_bits_out
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bool specific_tag;
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unsigned int tag_w;
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unsigned int access_mode;
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unsigned int obj_func_dyn_energy;
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unsigned int obj_func_dyn_power;
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unsigned int obj_func_leak_power;
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unsigned int obj_func_cycle_t;
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double F_sz_nm; // feature size in nm
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double F_sz_um; // feature size in um
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unsigned int num_rw_ports;
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unsigned int num_rd_ports;
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unsigned int num_wr_ports;
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unsigned int num_se_rd_ports; // number of single ended read ports
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unsigned int num_search_ports; // Sheng: number of search ports for CAM
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bool is_main_mem;
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bool is_cache;
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bool pure_ram;
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bool pure_cam;
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bool rpters_in_htree; // if there are repeaters in htree segment
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unsigned int ver_htree_wires_over_array;
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unsigned int broadcast_addr_din_over_ver_htrees;
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unsigned int temp;
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unsigned int ram_cell_tech_type;
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unsigned int peri_global_tech_type;
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unsigned int data_arr_ram_cell_tech_type;
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unsigned int data_arr_peri_global_tech_type;
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unsigned int tag_arr_ram_cell_tech_type;
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unsigned int tag_arr_peri_global_tech_type;
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unsigned int burst_len;
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unsigned int int_prefetch_w;
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unsigned int page_sz_bits;
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unsigned int ic_proj_type; // interconnect_projection_type
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unsigned int wire_is_mat_type; // wire_inside_mat_type
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unsigned int wire_os_mat_type; // wire_outside_mat_type
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enum Wire_type wt;
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int force_wiretype;
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bool print_input_args;
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unsigned int nuca_cache_sz; // TODO
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int ndbl, ndwl, nspd, ndsam1, ndsam2, ndcm;
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bool force_cache_config;
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int cache_level;
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int cores;
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int nuca_bank_count;
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int force_nuca_bank;
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int delay_wt, dynamic_power_wt, leakage_power_wt,
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cycle_time_wt, area_wt;
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int delay_wt_nuca, dynamic_power_wt_nuca, leakage_power_wt_nuca,
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cycle_time_wt_nuca, area_wt_nuca;
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int delay_dev, dynamic_power_dev, leakage_power_dev,
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cycle_time_dev, area_dev;
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int delay_dev_nuca, dynamic_power_dev_nuca, leakage_power_dev_nuca,
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cycle_time_dev_nuca, area_dev_nuca;
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int ed; //ED or ED2 optimization
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int nuca;
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bool fast_access;
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unsigned int block_sz; // bytes
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unsigned int tag_assoc;
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unsigned int data_assoc;
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bool is_seq_acc;
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bool fully_assoc;
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unsigned int nsets; // == number_of_sets
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int print_detail;
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bool add_ecc_b_;
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//parameters for design constraint
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double throughput;
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double latency;
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bool pipelinable;
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int pipeline_stages;
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int per_stage_vector;
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bool with_clock_grid;
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};
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typedef struct {
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int Ndwl;
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int Ndbl;
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double Nspd;
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int deg_bl_muxing;
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int Ndsam_lev_1;
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int Ndsam_lev_2;
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int number_activated_mats_horizontal_direction;
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int number_subbanks;
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int page_size_in_bits;
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double delay_route_to_bank;
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double delay_crossbar;
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double delay_addr_din_horizontal_htree;
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double delay_addr_din_vertical_htree;
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double delay_row_predecode_driver_and_block;
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double delay_row_decoder;
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double delay_bitlines;
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double delay_sense_amp;
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double delay_subarray_output_driver;
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double delay_bit_mux_predecode_driver_and_block;
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double delay_bit_mux_decoder;
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double delay_senseamp_mux_lev_1_predecode_driver_and_block;
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double delay_senseamp_mux_lev_1_decoder;
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double delay_senseamp_mux_lev_2_predecode_driver_and_block;
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double delay_senseamp_mux_lev_2_decoder;
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double delay_input_htree;
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double delay_output_htree;
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double delay_dout_vertical_htree;
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double delay_dout_horizontal_htree;
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double delay_comparator;
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double access_time;
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double cycle_time;
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double multisubbank_interleave_cycle_time;
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double delay_request_network;
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double delay_inside_mat;
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double delay_reply_network;
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double trcd;
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double cas_latency;
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double precharge_delay;
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powerDef power_routing_to_bank;
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powerDef power_addr_input_htree;
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powerDef power_data_input_htree;
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powerDef power_data_output_htree;
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powerDef power_addr_horizontal_htree;
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powerDef power_datain_horizontal_htree;
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powerDef power_dataout_horizontal_htree;
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powerDef power_addr_vertical_htree;
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powerDef power_datain_vertical_htree;
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powerDef power_row_predecoder_drivers;
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powerDef power_row_predecoder_blocks;
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powerDef power_row_decoders;
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powerDef power_bit_mux_predecoder_drivers;
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powerDef power_bit_mux_predecoder_blocks;
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powerDef power_bit_mux_decoders;
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powerDef power_senseamp_mux_lev_1_predecoder_drivers;
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powerDef power_senseamp_mux_lev_1_predecoder_blocks;
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powerDef power_senseamp_mux_lev_1_decoders;
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powerDef power_senseamp_mux_lev_2_predecoder_drivers;
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powerDef power_senseamp_mux_lev_2_predecoder_blocks;
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powerDef power_senseamp_mux_lev_2_decoders;
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powerDef power_bitlines;
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powerDef power_sense_amps;
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powerDef power_prechg_eq_drivers;
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powerDef power_output_drivers_at_subarray;
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powerDef power_dataout_vertical_htree;
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powerDef power_comparators;
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powerDef power_crossbar;
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powerDef total_power;
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double area;
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double all_banks_height;
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double all_banks_width;
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double bank_height;
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double bank_width;
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double subarray_memory_cell_area_height;
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double subarray_memory_cell_area_width;
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double mat_height;
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double mat_width;
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double routing_area_height_within_bank;
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double routing_area_width_within_bank;
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double area_efficiency;
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double refresh_power;
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double dram_refresh_period;
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double dram_array_availability;
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double dyn_read_energy_from_closed_page;
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double dyn_read_energy_from_open_page;
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double leak_power_subbank_closed_page;
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double leak_power_subbank_open_page;
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double leak_power_request_and_reply_networks;
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double activate_energy;
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double read_energy;
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double write_energy;
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double precharge_energy;
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} results_mem_array;
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class uca_org_t {
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public:
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mem_array * tag_array2;
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mem_array * data_array2;
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double access_time;
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double cycle_time;
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double area;
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double area_efficiency;
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powerDef power;
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double leak_power_with_sleep_transistors_in_mats;
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double cache_ht;
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double cache_len;
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char file_n[100];
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double vdd_periph_global;
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bool valid;
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results_mem_array tag_array;
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results_mem_array data_array;
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uca_org_t();
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void find_delay();
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void find_energy();
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void find_area();
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void find_cyc();
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void adjust_area();//for McPAT only to adjust routing overhead
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void cleanup();
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~uca_org_t() {};
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};
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void reconfigure(InputParameter *local_interface, uca_org_t *fin_res);
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uca_org_t cacti_interface(const string & infile_name);
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//McPAT's plain interface, please keep !!!
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uca_org_t cacti_interface(InputParameter * const local_interface);
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//McPAT's plain interface, please keep !!!
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uca_org_t init_interface(InputParameter * const local_interface,
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const string &name);
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//McPAT's plain interface, please keep !!!
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uca_org_t cacti_interface(
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int cache_size,
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int line_size,
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int associativity,
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int rw_ports,
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int excl_read_ports,
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int excl_write_ports,
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int single_ended_read_ports,
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int search_ports,
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int banks,
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double tech_node,
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int output_width,
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int specific_tag,
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int tag_width,
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int access_mode,
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int cache,
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int main_mem,
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int obj_func_delay,
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int obj_func_dynamic_power,
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int obj_func_leakage_power,
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int obj_func_cycle_time,
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int obj_func_area,
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int dev_func_delay,
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int dev_func_dynamic_power,
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int dev_func_leakage_power,
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int dev_func_area,
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int dev_func_cycle_time,
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int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate
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int temp,
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int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing
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int data_arr_ram_cell_tech_flavor_in,
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int data_arr_peri_global_tech_flavor_in,
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int tag_arr_ram_cell_tech_flavor_in,
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int tag_arr_peri_global_tech_flavor_in,
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int interconnect_projection_type_in,
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int wire_inside_mat_type_in,
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int wire_outside_mat_type_in,
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int REPEATERS_IN_HTREE_SEGMENTS_in,
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int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in,
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int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in,
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int PAGE_SIZE_BITS_in,
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int BURST_LENGTH_in,
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int INTERNAL_PREFETCH_WIDTH_in,
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int force_wiretype,
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int wiretype,
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int force_config,
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int ndwl,
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int ndbl,
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int nspd,
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int ndcm,
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int ndsam1,
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int ndsam2,
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int ecc);
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//Naveen's interface
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uca_org_t cacti_interface(
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int cache_size,
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int line_size,
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int associativity,
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int rw_ports,
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int excl_read_ports,
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int excl_write_ports,
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int single_ended_read_ports,
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int banks,
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double tech_node,
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int page_sz,
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int burst_length,
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int pre_width,
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int output_width,
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int specific_tag,
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int tag_width,
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int access_mode, //0 normal, 1 seq, 2 fast
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int cache, //scratch ram or cache
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int main_mem,
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int obj_func_delay,
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int obj_func_dynamic_power,
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int obj_func_leakage_power,
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int obj_func_area,
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int obj_func_cycle_time,
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int dev_func_delay,
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int dev_func_dynamic_power,
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int dev_func_leakage_power,
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int dev_func_area,
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int dev_func_cycle_time,
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int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate
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int temp,
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int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing
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int data_arr_ram_cell_tech_flavor_in,
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int data_arr_peri_global_tech_flavor_in,
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int tag_arr_ram_cell_tech_flavor_in,
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int tag_arr_peri_global_tech_flavor_in,
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int interconnect_projection_type_in, // 0 - aggressive, 1 - normal
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int wire_inside_mat_type_in,
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int wire_outside_mat_type_in,
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int is_nuca, // 0 - UCA, 1 - NUCA
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int core_count,
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int cache_level, // 0 - L2, 1 - L3
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int nuca_bank_count,
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int nuca_obj_func_delay,
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int nuca_obj_func_dynamic_power,
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int nuca_obj_func_leakage_power,
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int nuca_obj_func_area,
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int nuca_obj_func_cycle_time,
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int nuca_dev_func_delay,
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int nuca_dev_func_dynamic_power,
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int nuca_dev_func_leakage_power,
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int nuca_dev_func_area,
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int nuca_dev_func_cycle_time,
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int REPEATERS_IN_HTREE_SEGMENTS_in,//TODO for now only wires with repeaters are supported
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int p_input);
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class mem_array {
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public:
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int Ndcm;
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int Ndwl;
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int Ndbl;
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double Nspd;
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int deg_bl_muxing;
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int Ndsam_lev_1;
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int Ndsam_lev_2;
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double access_time;
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double cycle_time;
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double multisubbank_interleave_cycle_time;
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double area_ram_cells;
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double area;
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powerDef power;
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double delay_senseamp_mux_decoder;
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double delay_before_subarray_output_driver;
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double delay_from_subarray_output_driver_to_output;
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double height;
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double width;
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double mat_height;
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double mat_length;
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double subarray_length;
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double subarray_height;
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|
|
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double delay_route_to_bank,
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delay_input_htree,
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delay_row_predecode_driver_and_block,
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delay_row_decoder,
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delay_bitlines,
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delay_sense_amp,
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delay_subarray_output_driver,
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delay_dout_htree,
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|
delay_comparator,
|
|
delay_matchlines;
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|
|
|
double all_banks_height,
|
|
all_banks_width,
|
|
area_efficiency;
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|
|
|
powerDef power_routing_to_bank;
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|
powerDef power_addr_input_htree;
|
|
powerDef power_data_input_htree;
|
|
powerDef power_data_output_htree;
|
|
powerDef power_htree_in_search;
|
|
powerDef power_htree_out_search;
|
|
powerDef power_row_predecoder_drivers;
|
|
powerDef power_row_predecoder_blocks;
|
|
powerDef power_row_decoders;
|
|
powerDef power_bit_mux_predecoder_drivers;
|
|
powerDef power_bit_mux_predecoder_blocks;
|
|
powerDef power_bit_mux_decoders;
|
|
powerDef power_senseamp_mux_lev_1_predecoder_drivers;
|
|
powerDef power_senseamp_mux_lev_1_predecoder_blocks;
|
|
powerDef power_senseamp_mux_lev_1_decoders;
|
|
powerDef power_senseamp_mux_lev_2_predecoder_drivers;
|
|
powerDef power_senseamp_mux_lev_2_predecoder_blocks;
|
|
powerDef power_senseamp_mux_lev_2_decoders;
|
|
powerDef power_bitlines;
|
|
powerDef power_sense_amps;
|
|
powerDef power_prechg_eq_drivers;
|
|
powerDef power_output_drivers_at_subarray;
|
|
powerDef power_dataout_vertical_htree;
|
|
powerDef power_comparators;
|
|
|
|
powerDef power_cam_bitline_precharge_eq_drv;
|
|
powerDef power_searchline;
|
|
powerDef power_searchline_precharge;
|
|
powerDef power_matchlines;
|
|
powerDef power_matchline_precharge;
|
|
powerDef power_matchline_to_wordline_drv;
|
|
|
|
min_values_t *arr_min;
|
|
enum Wire_type wt;
|
|
|
|
// dram stats
|
|
double activate_energy, read_energy, write_energy, precharge_energy,
|
|
refresh_power, leak_power_subbank_closed_page, leak_power_subbank_open_page,
|
|
leak_power_request_and_reply_networks;
|
|
|
|
double precharge_delay;
|
|
|
|
static bool lt(const mem_array * m1, const mem_array * m2);
|
|
};
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|
|
|
|
|
#endif
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