8f8d09538f
after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.
SConscript:
add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
add nics to fs.py
cpu/cpu_exec_context.cc:
remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
use new methods for accessing packet data
dev/ide_disk.cc:
add some more dprintfs
dev/io_device.cc:
delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
dUpdate for new packet methods to access data
dev/ns_gige.cc:
Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
update for new memory system
dev/sinic.cc:
dev/sinic.hh:
Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
Add methods to access data instead of accessing it directly.
--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
357 lines
9.2 KiB
C++
357 lines
9.2 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DEV_SINIC_HH__
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#define __DEV_SINIC_HH__
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#include "base/inet.hh"
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#include "base/statistics.hh"
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#include "dev/etherint.hh"
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#include "dev/etherpkt.hh"
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#include "dev/io_device.hh"
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#include "dev/pcidev.hh"
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#include "dev/pktfifo.hh"
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#include "dev/sinicreg.hh"
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#include "sim/eventq.hh"
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namespace Sinic {
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class Interface;
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class Base : public PciDev
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{
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protected:
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bool rxEnable;
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bool txEnable;
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Tick clock;
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inline Tick cycles(int numCycles) const { return numCycles * clock; }
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protected:
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Tick intrDelay;
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Tick intrTick;
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bool cpuIntrEnable;
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bool cpuPendingIntr;
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void cpuIntrPost(Tick when);
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void cpuInterrupt();
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void cpuIntrClear();
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typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent;
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friend void IntrEvent::process();
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IntrEvent *intrEvent;
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Interface *interface;
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bool cpuIntrPending() const;
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void cpuIntrAck() { cpuIntrClear(); }
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/**
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* Serialization stuff
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*/
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public:
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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/**
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* Construction/Destruction/Parameters
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*/
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public:
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struct Params : public PciDev::Params
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{
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Tick clock;
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Tick intr_delay;
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};
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Base(Params *p);
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};
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class Device : public Base
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{
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protected:
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/** Receive State Machine States */
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enum RxState {
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rxIdle,
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rxFifoBlock,
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rxBeginCopy,
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rxCopy,
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rxCopyDone
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};
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/** Transmit State Machine states */
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enum TxState {
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txIdle,
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txFifoBlock,
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txBeginCopy,
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txCopy,
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txCopyDone
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};
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/** device register file */
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struct {
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uint32_t Config; // 0x00
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uint32_t Command; // 0x04
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uint32_t IntrStatus; // 0x08
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uint32_t IntrMask; // 0x0c
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uint32_t RxMaxCopy; // 0x10
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uint32_t TxMaxCopy; // 0x14
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uint32_t RxMaxIntr; // 0x18
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uint32_t Reserved0; // 0x1c
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uint32_t RxFifoSize; // 0x20
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uint32_t TxFifoSize; // 0x24
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uint32_t RxFifoMark; // 0x28
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uint32_t TxFifoMark; // 0x2c
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uint64_t RxData; // 0x30
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uint64_t RxDone; // 0x38
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uint64_t RxWait; // 0x40
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uint64_t TxData; // 0x48
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uint64_t TxDone; // 0x50
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uint64_t TxWait; // 0x58
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uint64_t HwAddr; // 0x60
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} regs;
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struct VirtualReg {
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uint64_t RxData;
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uint64_t RxDone;
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uint64_t TxData;
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uint64_t TxDone;
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PacketFifo::iterator rxPacket;
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int rxPacketOffset;
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int rxPacketBytes;
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uint64_t rxDoneData;
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VirtualReg()
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: RxData(0), RxDone(0), TxData(0), TxDone(0),
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rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0)
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{ }
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};
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typedef std::vector<VirtualReg> VirtualRegs;
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typedef std::list<int> VirtualList;
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VirtualRegs virtualRegs;
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VirtualList rxList;
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VirtualList txList;
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uint8_t ®Data8(Addr daddr) { return *((uint8_t *)®s + daddr); }
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uint32_t ®Data32(Addr daddr) { return *(uint32_t *)®Data8(daddr); }
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uint64_t ®Data64(Addr daddr) { return *(uint64_t *)®Data8(daddr); }
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protected:
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RxState rxState;
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PacketFifo rxFifo;
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PacketFifo::iterator rxFifoPtr;
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bool rxEmpty;
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Addr rxDmaAddr;
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uint8_t *rxDmaData;
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int rxDmaLen;
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TxState txState;
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PacketFifo txFifo;
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bool txFull;
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EthPacketPtr txPacket;
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int txPacketOffset;
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int txPacketBytes;
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Addr txDmaAddr;
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uint8_t *txDmaData;
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int txDmaLen;
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protected:
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void reset();
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void rxKick();
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Tick rxKickTick;
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typedef EventWrapper<Device, &Device::rxKick> RxKickEvent;
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friend void RxKickEvent::process();
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void txKick();
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Tick txKickTick;
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typedef EventWrapper<Device, &Device::txKick> TxKickEvent;
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friend void TxKickEvent::process();
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/**
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* Retransmit event
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*/
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void transmit();
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void txEventTransmit()
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{
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transmit();
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if (txState == txFifoBlock)
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txKick();
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}
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typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent;
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friend void TxEvent::process();
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TxEvent txEvent;
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void txDump() const;
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void rxDump() const;
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/**
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* receive address filter
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*/
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bool rxFilter(const EthPacketPtr &packet);
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/**
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* device configuration
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*/
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void changeConfig(uint32_t newconfig);
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void command(uint32_t command);
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/**
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* device ethernet interface
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*/
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public:
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bool recvPacket(EthPacketPtr packet);
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void transferDone();
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void setInterface(Interface *i) { assert(!interface); interface = i; }
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/**
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* DMA parameters
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*/
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protected:
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void rxDmaDone();
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friend class EventWrapper<Device, &Device::rxDmaDone>;
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EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent;
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void txDmaDone();
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friend class EventWrapper<Device, &Device::txDmaDone>;
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EventWrapper<Device, &Device::txDmaDone> txDmaEvent;
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Tick dmaReadDelay;
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Tick dmaReadFactor;
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Tick dmaWriteDelay;
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Tick dmaWriteFactor;
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/**
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* Interrupt management
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*/
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protected:
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void devIntrPost(uint32_t interrupts);
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void devIntrClear(uint32_t interrupts = Regs::Intr_All);
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void devIntrChangeMask(uint32_t newmask);
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/**
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* Memory Interface
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*/
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public:
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virtual Tick read(Packet &pkt);
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virtual Tick write(Packet &pkt);
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void prepareIO(int cpu, int index);
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void prepareRead(int cpu, int index);
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void prepareWrite(int cpu, int index);
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// Fault iprRead(Addr daddr, int cpu, uint64_t &result);
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/**
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* Statistics
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*/
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private:
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Stats::Scalar<> rxBytes;
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Stats::Formula rxBandwidth;
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Stats::Scalar<> rxPackets;
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Stats::Formula rxPacketRate;
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Stats::Scalar<> rxIpPackets;
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Stats::Scalar<> rxTcpPackets;
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Stats::Scalar<> rxUdpPackets;
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Stats::Scalar<> rxIpChecksums;
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Stats::Scalar<> rxTcpChecksums;
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Stats::Scalar<> rxUdpChecksums;
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Stats::Scalar<> txBytes;
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Stats::Formula txBandwidth;
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Stats::Formula totBandwidth;
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Stats::Formula totPackets;
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Stats::Formula totBytes;
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Stats::Formula totPacketRate;
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Stats::Scalar<> txPackets;
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Stats::Formula txPacketRate;
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Stats::Scalar<> txIpPackets;
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Stats::Scalar<> txTcpPackets;
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Stats::Scalar<> txUdpPackets;
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Stats::Scalar<> txIpChecksums;
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Stats::Scalar<> txTcpChecksums;
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Stats::Scalar<> txUdpChecksums;
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public:
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virtual void regStats();
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/**
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* Serialization stuff
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*/
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public:
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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/**
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* Construction/Destruction/Parameters
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*/
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public:
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struct Params : public Base::Params
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{
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Tick tx_delay;
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Tick rx_delay;
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bool rx_filter;
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Net::EthAddr eaddr;
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uint32_t rx_max_copy;
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uint32_t tx_max_copy;
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uint32_t rx_max_intr;
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uint32_t rx_fifo_size;
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uint32_t tx_fifo_size;
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uint32_t rx_fifo_threshold;
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uint32_t tx_fifo_threshold;
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Tick dma_read_delay;
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Tick dma_read_factor;
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Tick dma_write_delay;
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Tick dma_write_factor;
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bool rx_thread;
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bool tx_thread;
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bool rss;
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};
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protected:
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const Params *params() const { return (const Params *)_params; }
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public:
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Device(Params *params);
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~Device();
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};
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/*
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* Ethernet Interface for an Ethernet Device
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*/
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class Interface : public EtherInt
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{
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private:
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Device *dev;
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public:
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Interface(const std::string &name, Device *d)
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: EtherInt(name), dev(d) { dev->setInterface(this); }
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virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
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virtual void sendDone() { dev->transferDone(); }
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};
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/* namespace Sinic */ }
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#endif // __DEV_SINIC_HH__
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