2fb632dbda
branch prediction, and makes memory dependence work properly.
SConscript:
Added return address stack, tournament predictor.
cpu/base_cpu.cc:
Added debug break and print statements.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Comment out possibly unneeded variables.
cpu/beta_cpu/2bit_local_pred.cc:
2bit predictor no longer speculatively updates itself.
cpu/beta_cpu/alpha_dyn_inst.hh:
Comment formatting.
cpu/beta_cpu/alpha_full_cpu.hh:
Formatting
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Added new parameters for branch predictors, and IQ parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Register stats.
cpu/beta_cpu/alpha_params.hh:
Added parameters for IQ, branch predictors, and store sets.
cpu/beta_cpu/bpred_unit.cc:
Removed one class.
cpu/beta_cpu/bpred_unit.hh:
Add in RAS, stats. Changed branch predictor unit functionality
so that it holds a history of past branches so it can update, and also
hold a proper history of the RAS so it can be restored on branch
mispredicts.
cpu/beta_cpu/bpred_unit_impl.hh:
Added in stats, history of branches, RAS. Now bpred unit actually
modifies the instruction's predicted next PC.
cpu/beta_cpu/btb.cc:
Add in sanity checks.
cpu/beta_cpu/comm.hh:
Add in communication where needed, remove it where it's not.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/rename.hh:
cpu/beta_cpu/rename_impl.hh:
Add in stats.
cpu/beta_cpu/commit_impl.hh:
Stats, update what is sent back on branch mispredict.
cpu/beta_cpu/cpu_policy.hh:
Change the bpred unit being used.
cpu/beta_cpu/decode.hh:
cpu/beta_cpu/decode_impl.hh:
Stats.
cpu/beta_cpu/fetch.hh:
Stats, change squash so it can handle squashes from decode differently
than squashes from commit.
cpu/beta_cpu/fetch_impl.hh:
Add in stats. Change how a cache line is fetched. Update to work with
caches. Also have separate functions for different behavior if squash
is coming from decode vs commit.
cpu/beta_cpu/free_list.hh:
Remove some old comments.
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/full_cpu.hh:
Added function to remove instructions from back of instruction list
until a certain sequence number.
cpu/beta_cpu/iew.hh:
Stats, separate squashing behavior due to branches vs memory.
cpu/beta_cpu/iew_impl.hh:
Stats, separate squashing behavior for branches vs memory.
cpu/beta_cpu/inst_queue.cc:
Debug stuff
cpu/beta_cpu/inst_queue.hh:
Stats, change how mem dep unit works, debug stuff
cpu/beta_cpu/inst_queue_impl.hh:
Stats, change how mem dep unit works, debug stuff. Also add in
parameters that used to be hardcoded.
cpu/beta_cpu/mem_dep_unit.hh:
cpu/beta_cpu/mem_dep_unit_impl.hh:
Add in stats, change how memory dependence unit works. It now holds
the memory instructions that are waiting for their memory dependences
to resolve. It provides which instructions are ready directly to the
IQ.
cpu/beta_cpu/regfile.hh:
Fix up sanity checks.
cpu/beta_cpu/rename_map.cc:
Fix loop variable type.
cpu/beta_cpu/rob_impl.hh:
Remove intermediate DynInstPtr
cpu/beta_cpu/store_set.cc:
Add in debugging statements.
cpu/beta_cpu/store_set.hh:
Reorder function arguments to match the rest of the calls.
--HG--
extra : convert_revision : aabf9b1fecd1d743265dfc3b174d6159937c6f44
599 lines
15 KiB
C++
599 lines
15 KiB
C++
#ifndef __REGFILE_HH__
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#define __REGFILE_HH__
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// @todo: Destructor
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using namespace std;
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#include "arch/alpha/isa_traits.hh"
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#include "cpu/beta_cpu/comm.hh"
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// This really only depends on the ISA, and not the Impl. It might be nicer
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// to see if I can make it depend on nothing...
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// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,
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// and should go in the AlphaFullCPU.
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template <class Impl>
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class PhysRegFile
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{
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//Note that most of the definitions of the IntReg, FloatReg, etc. exist
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//within the Impl/ISA class and not within this PhysRegFile class.
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//Will need some way to allow stuff like swap_palshadow to access the
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//correct registers. Might require code changes to swap_palshadow and
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//other execution contexts.
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//Will make these registers public for now, but they probably should
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//be private eventually with some accessor functions.
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public:
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typedef typename Impl::ISA ISA;
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PhysRegFile(unsigned _numPhysicalIntRegs,
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unsigned _numPhysicalFloatRegs);
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//Everything below should be pretty well identical to the normal
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//register file that exists within AlphaISA class.
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//The duplication is unfortunate but it's better than having
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//different ways to access certain registers.
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//Add these in later when everything else is in place
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// void serialize(std::ostream &os);
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// void unserialize(Checkpoint *cp, const std::string §ion);
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uint64_t readIntReg(PhysRegIndex reg_idx)
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{
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assert(reg_idx < numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Access to int register %i, has data "
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"%i\n", int(reg_idx), intRegFile[reg_idx]);
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return intRegFile[reg_idx];
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}
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float readFloatRegSingle(PhysRegIndex reg_idx)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Access to float register %i as single, has "
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"data %8.8f\n", int(reg_idx), (float)floatRegFile[reg_idx].d);
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return (float)floatRegFile[reg_idx].d;
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}
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double readFloatRegDouble(PhysRegIndex reg_idx)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Access to float register %i as double, has "
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" data %8.8f\n", int(reg_idx), floatRegFile[reg_idx].d);
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return floatRegFile[reg_idx].d;
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}
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uint64_t readFloatRegInt(PhysRegIndex reg_idx)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Access to float register %i as int, has data "
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"%lli\n", int(reg_idx), floatRegFile[reg_idx].q);
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return floatRegFile[reg_idx].q;
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}
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void setIntReg(PhysRegIndex reg_idx, uint64_t val)
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{
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assert(reg_idx < numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n",
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int(reg_idx), val);
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intRegFile[reg_idx] = val;
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}
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void setFloatRegSingle(PhysRegIndex reg_idx, float val)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
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int(reg_idx), val);
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floatRegFile[reg_idx].d = (double)val;
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}
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void setFloatRegDouble(PhysRegIndex reg_idx, double val)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
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int(reg_idx), val);
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floatRegFile[reg_idx].d = val;
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}
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void setFloatRegInt(PhysRegIndex reg_idx, uint64_t val)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
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int(reg_idx), val);
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floatRegFile[reg_idx].q = val;
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}
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uint64_t readPC()
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{
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return pc;
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}
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void setPC(uint64_t val)
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{
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pc = val;
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}
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void setNextPC(uint64_t val)
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{
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npc = val;
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}
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//Consider leaving this stuff and below in some implementation specific
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//file as opposed to the general register file. Or have a derived class.
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uint64_t readUniq()
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{
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return miscRegs.uniq;
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}
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void setUniq(uint64_t val)
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{
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miscRegs.uniq = val;
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}
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uint64_t readFpcr()
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{
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return miscRegs.fpcr;
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}
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void setFpcr(uint64_t val)
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{
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miscRegs.fpcr = val;
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}
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#ifdef FULL_SYSTEM
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uint64_t readIpr(int idx, Fault &fault);
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Fault setIpr(int idx, uint64_t val);
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int readIntrFlag() { return intrflag; }
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void setIntrFlag(int val) { intrflag = val; }
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#endif
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// These should be private eventually, but will be public for now
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// so that I can hack around the initregs issue.
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public:
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/** (signed) integer register file. */
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IntReg *intRegFile;
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/** Floating point register file. */
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FloatReg *floatRegFile;
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/** Miscellaneous register file. */
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MiscRegFile miscRegs;
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Addr pc; // program counter
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Addr npc; // next-cycle program counter
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private:
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unsigned numPhysicalIntRegs;
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unsigned numPhysicalFloatRegs;
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};
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template <class Impl>
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PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
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unsigned _numPhysicalFloatRegs)
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: numPhysicalIntRegs(_numPhysicalIntRegs),
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numPhysicalFloatRegs(_numPhysicalFloatRegs)
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{
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intRegFile = new IntReg[numPhysicalIntRegs];
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floatRegFile = new FloatReg[numPhysicalFloatRegs];
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memset(intRegFile, 0, sizeof(*intRegFile));
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memset(floatRegFile, 0, sizeof(*floatRegFile));
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}
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#ifdef FULL_SYSTEM
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//Problem: This code doesn't make sense at the RegFile level because it
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//needs things such as the itb and dtb. Either put it at the CPU level or
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//the DynInst level.
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template <class Impl>
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uint64_t
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PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
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{
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uint64_t retval = 0; // return value, default 0
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switch (idx) {
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case ISA::IPR_PALtemp0:
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case ISA::IPR_PALtemp1:
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case ISA::IPR_PALtemp2:
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case ISA::IPR_PALtemp3:
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case ISA::IPR_PALtemp4:
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case ISA::IPR_PALtemp5:
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case ISA::IPR_PALtemp6:
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case ISA::IPR_PALtemp7:
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case ISA::IPR_PALtemp8:
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case ISA::IPR_PALtemp9:
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case ISA::IPR_PALtemp10:
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case ISA::IPR_PALtemp11:
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case ISA::IPR_PALtemp12:
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case ISA::IPR_PALtemp13:
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case ISA::IPR_PALtemp14:
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case ISA::IPR_PALtemp15:
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case ISA::IPR_PALtemp16:
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case ISA::IPR_PALtemp17:
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case ISA::IPR_PALtemp18:
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case ISA::IPR_PALtemp19:
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case ISA::IPR_PALtemp20:
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case ISA::IPR_PALtemp21:
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case ISA::IPR_PALtemp22:
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case ISA::IPR_PALtemp23:
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case ISA::IPR_PAL_BASE:
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case ISA::IPR_IVPTBR:
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case ISA::IPR_DC_MODE:
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case ISA::IPR_MAF_MODE:
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case ISA::IPR_ISR:
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case ISA::IPR_EXC_ADDR:
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case ISA::IPR_IC_PERR_STAT:
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case ISA::IPR_DC_PERR_STAT:
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case ISA::IPR_MCSR:
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case ISA::IPR_ASTRR:
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case ISA::IPR_ASTER:
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case ISA::IPR_SIRR:
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case ISA::IPR_ICSR:
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case ISA::IPR_ICM:
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case ISA::IPR_DTB_CM:
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case ISA::IPR_IPLR:
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case ISA::IPR_INTID:
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case ISA::IPR_PMCTR:
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// no side-effect
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retval = ipr[idx];
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break;
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case ISA::IPR_CC:
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retval |= ipr[idx] & ULL(0xffffffff00000000);
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retval |= curTick & ULL(0x00000000ffffffff);
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break;
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case ISA::IPR_VA:
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// SFX: unlocks interrupt status registers
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retval = ipr[idx];
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if (!misspeculating())
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regs.intrlock = false;
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break;
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case ISA::IPR_VA_FORM:
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case ISA::IPR_MM_STAT:
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case ISA::IPR_IFAULT_VA_FORM:
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case ISA::IPR_EXC_MASK:
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case ISA::IPR_EXC_SUM:
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retval = ipr[idx];
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break;
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case ISA::IPR_DTB_PTE:
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{
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ISA::PTE &pte = dtb->index(!misspeculating());
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retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
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retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
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retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
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retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
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retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
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retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
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retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
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}
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break;
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// write only registers
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case ISA::IPR_HWINT_CLR:
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case ISA::IPR_SL_XMIT:
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case ISA::IPR_DC_FLUSH:
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case ISA::IPR_IC_FLUSH:
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case ISA::IPR_ALT_MODE:
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case ISA::IPR_DTB_IA:
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case ISA::IPR_DTB_IAP:
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case ISA::IPR_ITB_IA:
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case ISA::IPR_ITB_IAP:
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fault = Unimplemented_Opcode_Fault;
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break;
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default:
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// invalid IPR
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fault = Unimplemented_Opcode_Fault;
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break;
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}
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return retval;
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}
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#ifdef DEBUG
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// Cause the simulator to break when changing to the following IPL
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int break_ipl = -1;
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#endif
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template <class Impl>
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Fault
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PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
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{
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uint64_t old;
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if (misspeculating())
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return No_Fault;
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switch (idx) {
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case ISA::IPR_PALtemp0:
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case ISA::IPR_PALtemp1:
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case ISA::IPR_PALtemp2:
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case ISA::IPR_PALtemp3:
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case ISA::IPR_PALtemp4:
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case ISA::IPR_PALtemp5:
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case ISA::IPR_PALtemp6:
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case ISA::IPR_PALtemp7:
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case ISA::IPR_PALtemp8:
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case ISA::IPR_PALtemp9:
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case ISA::IPR_PALtemp10:
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case ISA::IPR_PALtemp11:
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case ISA::IPR_PALtemp12:
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case ISA::IPR_PALtemp13:
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case ISA::IPR_PALtemp14:
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case ISA::IPR_PALtemp15:
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case ISA::IPR_PALtemp16:
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case ISA::IPR_PALtemp17:
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case ISA::IPR_PALtemp18:
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case ISA::IPR_PALtemp19:
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case ISA::IPR_PALtemp20:
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case ISA::IPR_PALtemp21:
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case ISA::IPR_PALtemp22:
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case ISA::IPR_PAL_BASE:
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case ISA::IPR_IC_PERR_STAT:
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case ISA::IPR_DC_PERR_STAT:
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case ISA::IPR_PMCTR:
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// write entire quad w/ no side-effect
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ipr[idx] = val;
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break;
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case ISA::IPR_CC_CTL:
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// This IPR resets the cycle counter. We assume this only
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// happens once... let's verify that.
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assert(ipr[idx] == 0);
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ipr[idx] = 1;
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break;
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case ISA::IPR_CC:
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// This IPR only writes the upper 64 bits. It's ok to write
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// all 64 here since we mask out the lower 32 in rpcc (see
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// isa_desc).
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ipr[idx] = val;
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break;
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case ISA::IPR_PALtemp23:
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// write entire quad w/ no side-effect
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old = ipr[idx];
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ipr[idx] = val;
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kernelStats.context(old, val);
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break;
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case ISA::IPR_DTB_PTE:
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// write entire quad w/ no side-effect, tag is forthcoming
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ipr[idx] = val;
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break;
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case ISA::IPR_EXC_ADDR:
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// second least significant bit in PC is always zero
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ipr[idx] = val & ~2;
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break;
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case ISA::IPR_ASTRR:
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case ISA::IPR_ASTER:
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// only write least significant four bits - privilege mask
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ipr[idx] = val & 0xf;
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break;
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case ISA::IPR_IPLR:
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#ifdef DEBUG
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if (break_ipl != -1 && break_ipl == (val & 0x1f))
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debug_break();
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#endif
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// only write least significant five bits - interrupt level
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ipr[idx] = val & 0x1f;
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kernelStats.swpipl(ipr[idx]);
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break;
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case ISA::IPR_DTB_CM:
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kernelStats.mode((val & 0x18) != 0);
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case ISA::IPR_ICM:
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// only write two mode bits - processor mode
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ipr[idx] = val & 0x18;
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break;
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case ISA::IPR_ALT_MODE:
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// only write two mode bits - processor mode
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ipr[idx] = val & 0x18;
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break;
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case ISA::IPR_MCSR:
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// more here after optimization...
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ipr[idx] = val;
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break;
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case ISA::IPR_SIRR:
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// only write software interrupt mask
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ipr[idx] = val & 0x7fff0;
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break;
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case ISA::IPR_ICSR:
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ipr[idx] = val & ULL(0xffffff0300);
|
|
break;
|
|
|
|
case ISA::IPR_IVPTBR:
|
|
case ISA::IPR_MVPTBR:
|
|
ipr[idx] = val & ULL(0xffffffffc0000000);
|
|
break;
|
|
|
|
case ISA::IPR_DC_TEST_CTL:
|
|
ipr[idx] = val & 0x1ffb;
|
|
break;
|
|
|
|
case ISA::IPR_DC_MODE:
|
|
case ISA::IPR_MAF_MODE:
|
|
ipr[idx] = val & 0x3f;
|
|
break;
|
|
|
|
case ISA::IPR_ITB_ASN:
|
|
ipr[idx] = val & 0x7f0;
|
|
break;
|
|
|
|
case ISA::IPR_DTB_ASN:
|
|
ipr[idx] = val & ULL(0xfe00000000000000);
|
|
break;
|
|
|
|
case ISA::IPR_EXC_SUM:
|
|
case ISA::IPR_EXC_MASK:
|
|
// any write to this register clears it
|
|
ipr[idx] = 0;
|
|
break;
|
|
|
|
case ISA::IPR_INTID:
|
|
case ISA::IPR_SL_RCV:
|
|
case ISA::IPR_MM_STAT:
|
|
case ISA::IPR_ITB_PTE_TEMP:
|
|
case ISA::IPR_DTB_PTE_TEMP:
|
|
// read-only registers
|
|
return Unimplemented_Opcode_Fault;
|
|
|
|
case ISA::IPR_HWINT_CLR:
|
|
case ISA::IPR_SL_XMIT:
|
|
case ISA::IPR_DC_FLUSH:
|
|
case ISA::IPR_IC_FLUSH:
|
|
// the following are write only
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case ISA::IPR_DTB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
dtb->flushAll();
|
|
break;
|
|
|
|
case ISA::IPR_DTB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
dtb->flushProcesses();
|
|
break;
|
|
|
|
case ISA::IPR_DTB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]));
|
|
break;
|
|
|
|
case ISA::IPR_DTB_TAG: {
|
|
struct ISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]);
|
|
pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
dtb->insert(val, pte);
|
|
}
|
|
break;
|
|
|
|
case ISA::IPR_ITB_PTE: {
|
|
struct ISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (ITB_PTE_GH(val) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = ITB_PTE_PPN(val);
|
|
pte.xre = ITB_PTE_XRE(val);
|
|
pte.xwe = 0;
|
|
pte.fonr = ITB_PTE_FONR(val);
|
|
pte.fonw = ITB_PTE_FONW(val);
|
|
pte.asma = ITB_PTE_ASMA(val);
|
|
pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
itb->insert(ipr[ISA::IPR_ITB_TAG], pte);
|
|
}
|
|
break;
|
|
|
|
case ISA::IPR_ITB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
itb->flushAll();
|
|
break;
|
|
|
|
case ISA::IPR_ITB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
itb->flushProcesses();
|
|
break;
|
|
|
|
case ISA::IPR_ITB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]));
|
|
break;
|
|
|
|
default:
|
|
// invalid IPR
|
|
return Unimplemented_Opcode_Fault;
|
|
}
|
|
|
|
// no error...
|
|
return No_Fault;
|
|
}
|
|
|
|
#endif // #ifdef FULL_SYSTEM
|
|
|
|
#endif // __REGFILE_HH__
|