2fb632dbda
branch prediction, and makes memory dependence work properly.
SConscript:
Added return address stack, tournament predictor.
cpu/base_cpu.cc:
Added debug break and print statements.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Comment out possibly unneeded variables.
cpu/beta_cpu/2bit_local_pred.cc:
2bit predictor no longer speculatively updates itself.
cpu/beta_cpu/alpha_dyn_inst.hh:
Comment formatting.
cpu/beta_cpu/alpha_full_cpu.hh:
Formatting
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Added new parameters for branch predictors, and IQ parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Register stats.
cpu/beta_cpu/alpha_params.hh:
Added parameters for IQ, branch predictors, and store sets.
cpu/beta_cpu/bpred_unit.cc:
Removed one class.
cpu/beta_cpu/bpred_unit.hh:
Add in RAS, stats. Changed branch predictor unit functionality
so that it holds a history of past branches so it can update, and also
hold a proper history of the RAS so it can be restored on branch
mispredicts.
cpu/beta_cpu/bpred_unit_impl.hh:
Added in stats, history of branches, RAS. Now bpred unit actually
modifies the instruction's predicted next PC.
cpu/beta_cpu/btb.cc:
Add in sanity checks.
cpu/beta_cpu/comm.hh:
Add in communication where needed, remove it where it's not.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/rename.hh:
cpu/beta_cpu/rename_impl.hh:
Add in stats.
cpu/beta_cpu/commit_impl.hh:
Stats, update what is sent back on branch mispredict.
cpu/beta_cpu/cpu_policy.hh:
Change the bpred unit being used.
cpu/beta_cpu/decode.hh:
cpu/beta_cpu/decode_impl.hh:
Stats.
cpu/beta_cpu/fetch.hh:
Stats, change squash so it can handle squashes from decode differently
than squashes from commit.
cpu/beta_cpu/fetch_impl.hh:
Add in stats. Change how a cache line is fetched. Update to work with
caches. Also have separate functions for different behavior if squash
is coming from decode vs commit.
cpu/beta_cpu/free_list.hh:
Remove some old comments.
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/full_cpu.hh:
Added function to remove instructions from back of instruction list
until a certain sequence number.
cpu/beta_cpu/iew.hh:
Stats, separate squashing behavior due to branches vs memory.
cpu/beta_cpu/iew_impl.hh:
Stats, separate squashing behavior for branches vs memory.
cpu/beta_cpu/inst_queue.cc:
Debug stuff
cpu/beta_cpu/inst_queue.hh:
Stats, change how mem dep unit works, debug stuff
cpu/beta_cpu/inst_queue_impl.hh:
Stats, change how mem dep unit works, debug stuff. Also add in
parameters that used to be hardcoded.
cpu/beta_cpu/mem_dep_unit.hh:
cpu/beta_cpu/mem_dep_unit_impl.hh:
Add in stats, change how memory dependence unit works. It now holds
the memory instructions that are waiting for their memory dependences
to resolve. It provides which instructions are ready directly to the
IQ.
cpu/beta_cpu/regfile.hh:
Fix up sanity checks.
cpu/beta_cpu/rename_map.cc:
Fix loop variable type.
cpu/beta_cpu/rob_impl.hh:
Remove intermediate DynInstPtr
cpu/beta_cpu/store_set.cc:
Add in debugging statements.
cpu/beta_cpu/store_set.hh:
Reorder function arguments to match the rest of the calls.
--HG--
extra : convert_revision : aabf9b1fecd1d743265dfc3b174d6159937c6f44
711 lines
19 KiB
C++
711 lines
19 KiB
C++
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#include "base/cprintf.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "mem/cache/cache.hh" // for dynamic cast
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#include "mem/mem_interface.hh"
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#include "sim/builder.hh"
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#include "sim/sim_events.hh"
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#include "sim/stats.hh"
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#include "cpu/beta_cpu/alpha_full_cpu.hh"
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#include "cpu/beta_cpu/alpha_params.hh"
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#include "cpu/beta_cpu/comm.hh"
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template <class Impl>
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AlphaFullCPU<Impl>::AlphaFullCPU(Params ¶ms)
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: FullBetaCPU<AlphaSimpleImpl>(params)
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{
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DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
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fetch.setCPU(this);
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decode.setCPU(this);
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rename.setCPU(this);
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iew.setCPU(this);
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commit.setCPU(this);
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rob.setCPU(this);
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::regStats()
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{
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// Register stats for everything that has stats.
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fullCPURegStats();
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fetch.regStats();
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decode.regStats();
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rename.regStats();
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iew.regStats();
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commit.regStats();
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}
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#ifndef FULL_SYSTEM
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template <class Impl>
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void
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AlphaFullCPU<Impl>::syscall()
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{
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DPRINTF(FullCPU, "AlphaFullCPU: Syscall() called.\n\n");
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// Commit stage needs to run as well.
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commit.tick();
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squashStages();
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// Temporarily increase this by one to account for the syscall
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// instruction.
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++funcExeInst;
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// Copy over all important state to xc once all the unrolling is done.
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copyToXC();
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process->syscall(xc);
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// Copy over all important state back to CPU.
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copyFromXC();
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// Decrease funcExeInst by one as the normal commit will handle
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// incrememnting it.
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--funcExeInst;
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}
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// This is not a pretty function, and should only be used if it is necessary
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// to fake having everything squash all at once (ie for non-full system
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// syscalls). Maybe put this at the FullCPU level?
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template <class Impl>
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void
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AlphaFullCPU<Impl>::squashStages()
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{
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InstSeqNum rob_head = rob.readHeadSeqNum();
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// Now hack the time buffer to put this sequence number in the places
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// where the stages might read it.
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for (int i = 0; i < 5; ++i)
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{
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timeBuffer.access(-i)->commitInfo.doneSeqNum = rob_head;
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}
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fetch.squash(rob.readHeadNextPC());
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fetchQueue.advance();
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decode.squash();
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decodeQueue.advance();
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rename.squash();
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renameQueue.advance();
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renameQueue.advance();
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// Be sure to advance the IEW queues so that the commit stage doesn't
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// try to set an instruction as completed at the same time that it
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// might be deleting it.
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iew.squash();
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iewQueue.advance();
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iewQueue.advance();
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rob.squash(rob_head);
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commit.setSquashing();
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// Now hack the time buffer to clear the sequence numbers in the places
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// where the stages might read it.?
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for (int i = 0; i < 5; ++i)
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{
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timeBuffer.access(-i)->commitInfo.doneSeqNum = 0;
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}
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}
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#endif // FULL_SYSTEM
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template <class Impl>
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void
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AlphaFullCPU<Impl>::copyToXC()
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{
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PhysRegIndex renamed_reg;
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// First loop through the integer registers.
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for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
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{
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renamed_reg = renameMap.lookup(i);
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xc->regs.intRegFile[i] = regFile.intRegFile[renamed_reg];
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DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n",
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renamed_reg, regFile.intRegFile[renamed_reg]);
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
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{
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renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
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xc->regs.floatRegFile.d[i] = regFile.floatRegFile[renamed_reg].d;
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xc->regs.floatRegFile.q[i] = regFile.floatRegFile[renamed_reg].q;
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}
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xc->regs.miscRegs.fpcr = regFile.miscRegs.fpcr;
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xc->regs.miscRegs.uniq = regFile.miscRegs.uniq;
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xc->regs.miscRegs.lock_flag = regFile.miscRegs.lock_flag;
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xc->regs.miscRegs.lock_addr = regFile.miscRegs.lock_addr;
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xc->regs.pc = rob.readHeadPC();
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xc->regs.npc = xc->regs.pc+4;
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xc->func_exe_inst = funcExeInst;
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}
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// This function will probably mess things up unless the ROB is empty and
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// there are no instructions in the pipeline.
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template <class Impl>
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void
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AlphaFullCPU<Impl>::copyFromXC()
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{
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PhysRegIndex renamed_reg;
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// First loop through the integer registers.
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for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
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{
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renamed_reg = renameMap.lookup(i);
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DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
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"now has data %lli.\n",
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renamed_reg, regFile.intRegFile[renamed_reg],
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xc->regs.intRegFile[i]);
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regFile.intRegFile[renamed_reg] = xc->regs.intRegFile[i];
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
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{
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renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
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regFile.floatRegFile[renamed_reg].d = xc->regs.floatRegFile.d[i];
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regFile.floatRegFile[renamed_reg].q = xc->regs.floatRegFile.q[i] ;
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}
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// Then loop through the misc registers.
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regFile.miscRegs.fpcr = xc->regs.miscRegs.fpcr;
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regFile.miscRegs.uniq = xc->regs.miscRegs.uniq;
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regFile.miscRegs.lock_flag = xc->regs.miscRegs.lock_flag;
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regFile.miscRegs.lock_addr = xc->regs.miscRegs.lock_addr;
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// Then finally set the PC and the next PC.
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// regFile.pc = xc->regs.pc;
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// regFile.npc = xc->regs.npc;
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funcExeInst = xc->func_exe_inst;
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}
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#ifdef FULL_SYSTEM
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template <class Impl>
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uint64_t *
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AlphaFullCPU<Impl>::getIpr()
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{
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return regFile.getIpr();
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}
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template <class Impl>
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uint64_t
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AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
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{
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uint64_t *ipr = getIpr();
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uint64_t retval = 0; // return value, default 0
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PALtemp23:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IVPTBR:
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case AlphaISA::IPR_DC_MODE:
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case AlphaISA::IPR_MAF_MODE:
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case AlphaISA::IPR_ISR:
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case AlphaISA::IPR_EXC_ADDR:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_MCSR:
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case AlphaISA::IPR_ASTRR:
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case AlphaISA::IPR_ASTER:
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case AlphaISA::IPR_SIRR:
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case AlphaISA::IPR_ICSR:
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case AlphaISA::IPR_ICM:
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case AlphaISA::IPR_DTB_CM:
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case AlphaISA::IPR_IPLR:
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case AlphaISA::IPR_INTID:
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case AlphaISA::IPR_PMCTR:
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// no side-effect
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_CC:
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retval |= ipr[idx] & ULL(0xffffffff00000000);
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retval |= curTick & ULL(0x00000000ffffffff);
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break;
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case AlphaISA::IPR_VA:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_VA_FORM:
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case AlphaISA::IPR_MM_STAT:
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case AlphaISA::IPR_IFAULT_VA_FORM:
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case AlphaISA::IPR_EXC_MASK:
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case AlphaISA::IPR_EXC_SUM:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_DTB_PTE:
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{
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AlphaISA::PTE &pte = dtb->index(!misspeculating());
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retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
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retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
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retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
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retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
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retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
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retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
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retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
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}
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break;
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// write only registers
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case AlphaISA::IPR_HWINT_CLR:
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case AlphaISA::IPR_SL_XMIT:
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case AlphaISA::IPR_DC_FLUSH:
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case AlphaISA::IPR_IC_FLUSH:
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case AlphaISA::IPR_ALT_MODE:
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case AlphaISA::IPR_DTB_IA:
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case AlphaISA::IPR_DTB_IAP:
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case AlphaISA::IPR_ITB_IA:
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case AlphaISA::IPR_ITB_IAP:
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fault = Unimplemented_Opcode_Fault;
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break;
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default:
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// invalid IPR
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fault = Unimplemented_Opcode_Fault;
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break;
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}
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return retval;
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}
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template <class Impl>
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Fault
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AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
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{
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uint64_t *ipr = getIpr();
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uint64_t old;
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if (misspeculating())
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return No_Fault;
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_PMCTR:
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// write entire quad w/ no side-effect
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_CC_CTL:
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// This IPR resets the cycle counter. We assume this only
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// happens once... let's verify that.
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assert(ipr[idx] == 0);
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ipr[idx] = 1;
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break;
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case AlphaISA::IPR_CC:
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// This IPR only writes the upper 64 bits. It's ok to write
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// all 64 here since we mask out the lower 32 in rpcc (see
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// isa_desc).
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_PALtemp23:
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// write entire quad w/ no side-effect
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old = ipr[idx];
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ipr[idx] = val;
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kernelStats.context(old, val);
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break;
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case AlphaISA::IPR_DTB_PTE:
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// write entire quad w/ no side-effect, tag is forthcoming
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_EXC_ADDR:
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// second least significant bit in PC is always zero
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ipr[idx] = val & ~2;
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break;
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case AlphaISA::IPR_ASTRR:
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case AlphaISA::IPR_ASTER:
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// only write least significant four bits - privilege mask
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ipr[idx] = val & 0xf;
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break;
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case AlphaISA::IPR_IPLR:
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#ifdef DEBUG
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if (break_ipl != -1 && break_ipl == (val & 0x1f))
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debug_break();
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#endif
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// only write least significant five bits - interrupt level
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ipr[idx] = val & 0x1f;
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kernelStats.swpipl(ipr[idx]);
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break;
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case AlphaISA::IPR_DTB_CM:
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kernelStats.mode((val & 0x18) != 0);
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case AlphaISA::IPR_ICM:
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// only write two mode bits - processor mode
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ipr[idx] = val & 0x18;
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break;
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case AlphaISA::IPR_ALT_MODE:
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// only write two mode bits - processor mode
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ipr[idx] = val & 0x18;
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break;
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case AlphaISA::IPR_MCSR:
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// more here after optimization...
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_SIRR:
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// only write software interrupt mask
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ipr[idx] = val & 0x7fff0;
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break;
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case AlphaISA::IPR_ICSR:
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ipr[idx] = val & ULL(0xffffff0300);
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break;
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case AlphaISA::IPR_IVPTBR:
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case AlphaISA::IPR_MVPTBR:
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ipr[idx] = val & ULL(0xffffffffc0000000);
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break;
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case AlphaISA::IPR_DC_TEST_CTL:
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ipr[idx] = val & 0x1ffb;
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break;
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case AlphaISA::IPR_DC_MODE:
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case AlphaISA::IPR_MAF_MODE:
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ipr[idx] = val & 0x3f;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_ASN:
|
|
ipr[idx] = val & 0x7f0;
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_ASN:
|
|
ipr[idx] = val & ULL(0xfe00000000000000);
|
|
break;
|
|
|
|
case AlphaISA::IPR_EXC_SUM:
|
|
case AlphaISA::IPR_EXC_MASK:
|
|
// any write to this register clears it
|
|
ipr[idx] = 0;
|
|
break;
|
|
|
|
case AlphaISA::IPR_INTID:
|
|
case AlphaISA::IPR_SL_RCV:
|
|
case AlphaISA::IPR_MM_STAT:
|
|
case AlphaISA::IPR_ITB_PTE_TEMP:
|
|
case AlphaISA::IPR_DTB_PTE_TEMP:
|
|
// read-only registers
|
|
return Unimplemented_Opcode_Fault;
|
|
|
|
case AlphaISA::IPR_HWINT_CLR:
|
|
case AlphaISA::IPR_SL_XMIT:
|
|
case AlphaISA::IPR_DC_FLUSH:
|
|
case AlphaISA::IPR_IC_FLUSH:
|
|
// the following are write only
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
dtb->flushAll();
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
dtb->flushProcesses();
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_TAG: {
|
|
struct AlphaISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
dtb->insert(val, pte);
|
|
}
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_PTE: {
|
|
struct AlphaISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (ITB_PTE_GH(val) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = ITB_PTE_PPN(val);
|
|
pte.xre = ITB_PTE_XRE(val);
|
|
pte.xwe = 0;
|
|
pte.fonr = ITB_PTE_FONR(val);
|
|
pte.fonw = ITB_PTE_FONW(val);
|
|
pte.asma = ITB_PTE_ASMA(val);
|
|
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
|
|
}
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
itb->flushAll();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
itb->flushProcesses();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
|
|
break;
|
|
|
|
default:
|
|
// invalid IPR
|
|
return Unimplemented_Opcode_Fault;
|
|
}
|
|
|
|
// no error...
|
|
return No_Fault;
|
|
|
|
}
|
|
|
|
template <class Impl>
|
|
int
|
|
AlphaFullCPU<Impl>::readIntrFlag()
|
|
{
|
|
return regs.intrflag;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::setIntrFlag(int val)
|
|
{
|
|
regs.intrflag = val;
|
|
}
|
|
|
|
// Can force commit stage to squash and stuff.
|
|
template <class Impl>
|
|
Fault
|
|
AlphaFullCPU<Impl>::hwrei()
|
|
{
|
|
uint64_t *ipr = getIpr();
|
|
|
|
if (!PC_PAL(regs.pc))
|
|
return Unimplemented_Opcode_Fault;
|
|
|
|
setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
|
|
|
|
if (!misspeculating()) {
|
|
kernelStats.hwrei();
|
|
|
|
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
|
|
AlphaISA::swap_palshadow(®s, false);
|
|
|
|
AlphaISA::check_interrupts = true;
|
|
}
|
|
|
|
// FIXME: XXX check for interrupts? XXX
|
|
return No_Fault;
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
AlphaFullCPU<Impl>::inPalMode()
|
|
{
|
|
return PC_PAL(readPC());
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
AlphaFullCPU<Impl>::simPalCheck(int palFunc)
|
|
{
|
|
kernelStats.callpal(palFunc);
|
|
|
|
switch (palFunc) {
|
|
case PAL::halt:
|
|
halt();
|
|
if (--System::numSystemsRunning == 0)
|
|
new SimExitEvent("all cpus halted");
|
|
break;
|
|
|
|
case PAL::bpt:
|
|
case PAL::bugchk:
|
|
if (system->breakpoint())
|
|
return false;
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
// Probably shouldn't be able to switch to the trap handler as quickly as
|
|
// this. Also needs to get the exception restart address from the commit
|
|
// stage.
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::trap(Fault fault)
|
|
{
|
|
uint64_t PC = commit.readPC();
|
|
|
|
DPRINTF(Fault, "Fault %s\n", FaultName(fault));
|
|
Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
|
|
|
|
assert(!misspeculating());
|
|
kernelStats.fault(fault);
|
|
|
|
if (fault == Arithmetic_Fault)
|
|
panic("Arithmetic traps are unimplemented!");
|
|
|
|
AlphaISA::InternalProcReg *ipr = getIpr();
|
|
|
|
// exception restart address - Get the commit PC
|
|
if (fault != Interrupt_Fault || !PC_PAL(PC))
|
|
ipr[AlphaISA::IPR_EXC_ADDR] = PC;
|
|
|
|
if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
|
|
fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
|
|
// traps... skip faulting instruction
|
|
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
|
|
}
|
|
|
|
if (!PC_PAL(PC))
|
|
AlphaISA::swap_palshadow(®s, true);
|
|
|
|
setPC( ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault] );
|
|
setNextPC(PC + sizeof(MachInst));
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::processInterrupts()
|
|
{
|
|
// Check for interrupts here. For now can copy the code that exists
|
|
// within isa_fullsys_traits.hh.
|
|
}
|
|
|
|
// swap_palshadow swaps in the values of the shadow registers and
|
|
// swaps them with the values of the physical registers that map to the
|
|
// same logical index.
|
|
template <class Impl>
|
|
void
|
|
AlphaFullCPU<Impl>::swap_palshadow(RegFile *regs, bool use_shadow)
|
|
{
|
|
if (palShadowEnabled == use_shadow)
|
|
panic("swap_palshadow: wrong PAL shadow state");
|
|
|
|
palShadowEnabled = use_shadow;
|
|
|
|
// Will have to lookup in rename map to get physical registers, then
|
|
// swap.
|
|
for (int i = 0; i < AlphaISA::NumIntRegs; i++) {
|
|
if (reg_redir[i]) {
|
|
AlphaISA::IntReg temp = regs->intRegFile[i];
|
|
regs->intRegFile[i] = regs->palregs[i];
|
|
regs->palregs[i] = temp;
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif // FULL_SYSTEM
|