2fb632dbda
branch prediction, and makes memory dependence work properly.
SConscript:
Added return address stack, tournament predictor.
cpu/base_cpu.cc:
Added debug break and print statements.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Comment out possibly unneeded variables.
cpu/beta_cpu/2bit_local_pred.cc:
2bit predictor no longer speculatively updates itself.
cpu/beta_cpu/alpha_dyn_inst.hh:
Comment formatting.
cpu/beta_cpu/alpha_full_cpu.hh:
Formatting
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Added new parameters for branch predictors, and IQ parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Register stats.
cpu/beta_cpu/alpha_params.hh:
Added parameters for IQ, branch predictors, and store sets.
cpu/beta_cpu/bpred_unit.cc:
Removed one class.
cpu/beta_cpu/bpred_unit.hh:
Add in RAS, stats. Changed branch predictor unit functionality
so that it holds a history of past branches so it can update, and also
hold a proper history of the RAS so it can be restored on branch
mispredicts.
cpu/beta_cpu/bpred_unit_impl.hh:
Added in stats, history of branches, RAS. Now bpred unit actually
modifies the instruction's predicted next PC.
cpu/beta_cpu/btb.cc:
Add in sanity checks.
cpu/beta_cpu/comm.hh:
Add in communication where needed, remove it where it's not.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/rename.hh:
cpu/beta_cpu/rename_impl.hh:
Add in stats.
cpu/beta_cpu/commit_impl.hh:
Stats, update what is sent back on branch mispredict.
cpu/beta_cpu/cpu_policy.hh:
Change the bpred unit being used.
cpu/beta_cpu/decode.hh:
cpu/beta_cpu/decode_impl.hh:
Stats.
cpu/beta_cpu/fetch.hh:
Stats, change squash so it can handle squashes from decode differently
than squashes from commit.
cpu/beta_cpu/fetch_impl.hh:
Add in stats. Change how a cache line is fetched. Update to work with
caches. Also have separate functions for different behavior if squash
is coming from decode vs commit.
cpu/beta_cpu/free_list.hh:
Remove some old comments.
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/full_cpu.hh:
Added function to remove instructions from back of instruction list
until a certain sequence number.
cpu/beta_cpu/iew.hh:
Stats, separate squashing behavior due to branches vs memory.
cpu/beta_cpu/iew_impl.hh:
Stats, separate squashing behavior for branches vs memory.
cpu/beta_cpu/inst_queue.cc:
Debug stuff
cpu/beta_cpu/inst_queue.hh:
Stats, change how mem dep unit works, debug stuff
cpu/beta_cpu/inst_queue_impl.hh:
Stats, change how mem dep unit works, debug stuff. Also add in
parameters that used to be hardcoded.
cpu/beta_cpu/mem_dep_unit.hh:
cpu/beta_cpu/mem_dep_unit_impl.hh:
Add in stats, change how memory dependence unit works. It now holds
the memory instructions that are waiting for their memory dependences
to resolve. It provides which instructions are ready directly to the
IQ.
cpu/beta_cpu/regfile.hh:
Fix up sanity checks.
cpu/beta_cpu/rename_map.cc:
Fix loop variable type.
cpu/beta_cpu/rob_impl.hh:
Remove intermediate DynInstPtr
cpu/beta_cpu/store_set.cc:
Add in debugging statements.
cpu/beta_cpu/store_set.hh:
Reorder function arguments to match the rest of the calls.
--HG--
extra : convert_revision : aabf9b1fecd1d743265dfc3b174d6159937c6f44
80 lines
2.1 KiB
C++
80 lines
2.1 KiB
C++
//Todo:
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#ifndef __ALPHA_DYN_INST_HH__
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#define __ALPHA_DYN_INST_HH__
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/beta_cpu/alpha_full_cpu.hh"
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#include "cpu/beta_cpu/alpha_impl.hh"
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#include "cpu/inst_seq.hh"
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/**
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* Mostly implementation specific AlphaDynInst. It is templated in case there
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* are other implementations that are similar enough to be able to use this
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* class without changes. This is mainly useful if there are multiple similar
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* CPU implementations of the same ISA.
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*/
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template <class Impl>
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class AlphaDynInst : public BaseDynInst<Impl>
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{
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public:
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/** Typedef for the CPU. */
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typedef typename Impl::FullCPU FullCPU;
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/** Typedef to get the ISA. */
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typedef typename Impl::ISA ISA;
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/** Binary machine instruction type. */
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typedef typename ISA::MachInst MachInst;
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/** Memory address type. */
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typedef typename ISA::Addr Addr;
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/** Logical register index type. */
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typedef typename ISA::RegIndex RegIndex;
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/** Integer register index type. */
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typedef typename ISA::IntReg IntReg;
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enum {
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MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
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MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
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};
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public:
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/** BaseDynInst constructor given a binary instruction. */
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AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
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FullCPU *cpu);
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/** BaseDynInst constructor given a static inst pointer. */
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AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
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/** Executes the instruction. */
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Fault execute()
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{
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fault = staticInst->execute(this, traceData);
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return fault;
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}
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public:
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uint64_t readUniq();
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void setUniq(uint64_t val);
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uint64_t readFpcr();
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void setFpcr(uint64_t val);
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#ifdef FULL_SYSTEM
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uint64_t readIpr(int idx, Fault &fault);
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Fault setIpr(int idx, uint64_t val);
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Fault hwrei();
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int readIntrFlag();
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void setIntrFlag(int val);
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bool inPalMode();
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void trap(Fault fault);
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bool simPalCheck(int palFunc);
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#else
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void syscall();
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#endif
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};
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#endif // __ALPHA_DYN_INST_HH__
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