2fb632dbda
branch prediction, and makes memory dependence work properly.
SConscript:
Added return address stack, tournament predictor.
cpu/base_cpu.cc:
Added debug break and print statements.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Comment out possibly unneeded variables.
cpu/beta_cpu/2bit_local_pred.cc:
2bit predictor no longer speculatively updates itself.
cpu/beta_cpu/alpha_dyn_inst.hh:
Comment formatting.
cpu/beta_cpu/alpha_full_cpu.hh:
Formatting
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Added new parameters for branch predictors, and IQ parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Register stats.
cpu/beta_cpu/alpha_params.hh:
Added parameters for IQ, branch predictors, and store sets.
cpu/beta_cpu/bpred_unit.cc:
Removed one class.
cpu/beta_cpu/bpred_unit.hh:
Add in RAS, stats. Changed branch predictor unit functionality
so that it holds a history of past branches so it can update, and also
hold a proper history of the RAS so it can be restored on branch
mispredicts.
cpu/beta_cpu/bpred_unit_impl.hh:
Added in stats, history of branches, RAS. Now bpred unit actually
modifies the instruction's predicted next PC.
cpu/beta_cpu/btb.cc:
Add in sanity checks.
cpu/beta_cpu/comm.hh:
Add in communication where needed, remove it where it's not.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/rename.hh:
cpu/beta_cpu/rename_impl.hh:
Add in stats.
cpu/beta_cpu/commit_impl.hh:
Stats, update what is sent back on branch mispredict.
cpu/beta_cpu/cpu_policy.hh:
Change the bpred unit being used.
cpu/beta_cpu/decode.hh:
cpu/beta_cpu/decode_impl.hh:
Stats.
cpu/beta_cpu/fetch.hh:
Stats, change squash so it can handle squashes from decode differently
than squashes from commit.
cpu/beta_cpu/fetch_impl.hh:
Add in stats. Change how a cache line is fetched. Update to work with
caches. Also have separate functions for different behavior if squash
is coming from decode vs commit.
cpu/beta_cpu/free_list.hh:
Remove some old comments.
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/full_cpu.hh:
Added function to remove instructions from back of instruction list
until a certain sequence number.
cpu/beta_cpu/iew.hh:
Stats, separate squashing behavior due to branches vs memory.
cpu/beta_cpu/iew_impl.hh:
Stats, separate squashing behavior for branches vs memory.
cpu/beta_cpu/inst_queue.cc:
Debug stuff
cpu/beta_cpu/inst_queue.hh:
Stats, change how mem dep unit works, debug stuff
cpu/beta_cpu/inst_queue_impl.hh:
Stats, change how mem dep unit works, debug stuff. Also add in
parameters that used to be hardcoded.
cpu/beta_cpu/mem_dep_unit.hh:
cpu/beta_cpu/mem_dep_unit_impl.hh:
Add in stats, change how memory dependence unit works. It now holds
the memory instructions that are waiting for their memory dependences
to resolve. It provides which instructions are ready directly to the
IQ.
cpu/beta_cpu/regfile.hh:
Fix up sanity checks.
cpu/beta_cpu/rename_map.cc:
Fix loop variable type.
cpu/beta_cpu/rob_impl.hh:
Remove intermediate DynInstPtr
cpu/beta_cpu/store_set.cc:
Add in debugging statements.
cpu/beta_cpu/store_set.hh:
Reorder function arguments to match the rest of the calls.
--HG--
extra : convert_revision : aabf9b1fecd1d743265dfc3b174d6159937c6f44
507 lines
14 KiB
Python
507 lines
14 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2004 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import os
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import sys
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# This file defines how to build a particular configuration of M5
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# based on variable settings in the 'env' build environment.
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# Import build environment variable from SConstruct.
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Import('env')
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###################################################
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#
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# Define needed sources.
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#
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###################################################
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# Base sources used by all configurations.
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base_sources = Split('''
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arch/alpha/decoder.cc
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arch/alpha/alpha_full_cpu_exec.cc
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arch/alpha/fast_cpu_exec.cc
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arch/alpha/simple_cpu_exec.cc
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arch/alpha/full_cpu_exec.cc
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arch/alpha/faults.cc
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arch/alpha/isa_traits.cc
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base/circlebuf.cc
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base/copyright.cc
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base/cprintf.cc
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base/fast_alloc.cc
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base/fifo_buffer.cc
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base/hostinfo.cc
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base/hybrid_pred.cc
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base/inifile.cc
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base/intmath.cc
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base/match.cc
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base/misc.cc
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base/pollevent.cc
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base/python.cc
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base/range.cc
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base/sat_counter.cc
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base/socket.cc
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base/statistics.cc
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base/str.cc
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base/time.cc
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base/trace.cc
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base/traceflags.cc
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base/userinfo.cc
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base/compression/lzss_compression.cc
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base/loader/aout_object.cc
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base/loader/ecoff_object.cc
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base/loader/elf_object.cc
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base/loader/object_file.cc
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base/loader/symtab.cc
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base/stats/events.cc
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base/stats/python.cc
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base/stats/statdb.cc
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base/stats/visit.cc
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base/stats/text.cc
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cpu/base_cpu.cc
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cpu/base_dyn_inst.cc
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cpu/exec_context.cc
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cpu/exetrace.cc
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cpu/pc_event.cc
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cpu/static_inst.cc
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cpu/beta_cpu/2bit_local_pred.cc
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cpu/beta_cpu/alpha_dyn_inst.cc
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cpu/beta_cpu/alpha_full_cpu.cc
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cpu/beta_cpu/alpha_full_cpu_builder.cc
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cpu/beta_cpu/bpred_unit.cc
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cpu/beta_cpu/btb.cc
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cpu/beta_cpu/commit.cc
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cpu/beta_cpu/decode.cc
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cpu/beta_cpu/fetch.cc
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cpu/beta_cpu/free_list.cc
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cpu/beta_cpu/full_cpu.cc
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cpu/beta_cpu/iew.cc
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cpu/beta_cpu/inst_queue.cc
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cpu/beta_cpu/ldstq.cc
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cpu/beta_cpu/mem_dep_unit.cc
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cpu/beta_cpu/ras.cc
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cpu/beta_cpu/rename.cc
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cpu/beta_cpu/rename_map.cc
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cpu/beta_cpu/rob.cc
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cpu/beta_cpu/store_set.cc
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cpu/beta_cpu/tournament_pred.cc
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cpu/fast_cpu/fast_cpu.cc
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cpu/full_cpu/bpred.cc
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cpu/full_cpu/commit.cc
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cpu/full_cpu/create_vector.cc
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cpu/full_cpu/cv_spec_state.cc
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cpu/full_cpu/dd_queue.cc
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cpu/full_cpu/dep_link.cc
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cpu/full_cpu/dispatch.cc
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cpu/full_cpu/dyn_inst.cc
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cpu/full_cpu/execute.cc
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cpu/full_cpu/fetch.cc
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cpu/full_cpu/floss_reasons.cc
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cpu/full_cpu/fu_pool.cc
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cpu/full_cpu/full_cpu.cc
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cpu/full_cpu/inst_fifo.cc
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cpu/full_cpu/instpipe.cc
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cpu/full_cpu/issue.cc
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cpu/full_cpu/ls_queue.cc
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cpu/full_cpu/machine_queue.cc
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cpu/full_cpu/pipetrace.cc
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cpu/full_cpu/readyq.cc
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cpu/full_cpu/reg_info.cc
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cpu/full_cpu/rob_station.cc
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cpu/full_cpu/spec_memory.cc
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cpu/full_cpu/spec_state.cc
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cpu/full_cpu/storebuffer.cc
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cpu/full_cpu/writeback.cc
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cpu/full_cpu/iq/iq_station.cc
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cpu/full_cpu/iq/iqueue.cc
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cpu/full_cpu/iq/segmented/chain_info.cc
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cpu/full_cpu/iq/segmented/chain_wire.cc
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cpu/full_cpu/iq/segmented/iq_seg.cc
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cpu/full_cpu/iq/segmented/iq_segmented.cc
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cpu/full_cpu/iq/segmented/seg_chain.cc
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cpu/full_cpu/iq/seznec/iq_seznec.cc
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cpu/full_cpu/iq/standard/iq_standard.cc
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cpu/sampling_cpu/sampling_cpu.cc
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cpu/simple_cpu/simple_cpu.cc
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cpu/trace/reader/mem_trace_reader.cc
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cpu/trace/reader/ibm_reader.cc
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cpu/trace/reader/itx_reader.cc
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cpu/trace/reader/m5_reader.cc
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mem/base_hier.cc
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mem/base_mem.cc
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mem/hier_params.cc
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mem/mem_cmd.cc
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mem/mem_debug.cc
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mem/mem_req.cc
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mem/memory_interface.cc
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mem/bus/base_interface.cc
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mem/bus/bus.cc
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mem/bus/bus_bridge.cc
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mem/bus/bus_bridge_master.cc
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mem/bus/bus_bridge_slave.cc
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mem/bus/bus_interface.cc
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mem/bus/dma_bus_interface.cc
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mem/bus/dma_interface.cc
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mem/bus/master_interface.cc
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mem/bus/slave_interface.cc
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mem/cache/base_cache.cc
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mem/cache/cache.cc
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mem/cache/cache_builder.cc
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mem/cache/coherence/coherence_protocol.cc
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mem/cache/coherence/uni_coherence.cc
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mem/cache/miss/blocking_buffer.cc
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mem/cache/miss/miss_queue.cc
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mem/cache/miss/mshr.cc
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mem/cache/miss/mshr_queue.cc
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mem/cache/tags/base_tags.cc
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mem/cache/tags/cache_tags.cc
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mem/cache/tags/fa_lru.cc
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mem/cache/tags/iic.cc
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mem/cache/tags/lru.cc
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mem/cache/tags/split.cc
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mem/cache/tags/split_lifo.cc
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mem/cache/tags/split_lru.cc
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mem/cache/tags/repl/gen.cc
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mem/cache/tags/repl/repl.cc
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mem/functional_mem/functional_memory.cc
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mem/functional_mem/main_memory.cc
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mem/timing_mem/base_memory.cc
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mem/timing_mem/memory_builder.cc
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mem/timing_mem/simple_mem_bank.cc
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mem/trace/mem_trace_writer.cc
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mem/trace/m5_writer.cc
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sim/builder.cc
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sim/configfile.cc
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sim/debug.cc
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sim/eventq.cc
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sim/main.cc
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sim/param.cc
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sim/profile.cc
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sim/serialize.cc
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sim/sim_events.cc
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sim/sim_exit.cc
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sim/sim_init.cc
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sim/sim_object.cc
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sim/stat_context.cc
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sim/stat_control.cc
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sim/sw_context.cc
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sim/trace_context.cc
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sim/universe.cc
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sim/pyconfig/pyconfig.cc
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sim/pyconfig/code.cc
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''')
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base_obj_desc_files = Split('''
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cpu/full_cpu/iq/segmented/SegmentedIQ.od
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cpu/full_cpu/iq/seznec/SeznecIQ.od
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cpu/full_cpu/iq/standard/StandardIQ.od
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cpu/full_cpu/iq/BaseIQ.od
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cpu/full_cpu/BranchPred.od
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cpu/full_cpu/FUDesc.od
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cpu/full_cpu/FullCPU.od
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cpu/full_cpu/FuncUnitPool.od
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cpu/full_cpu/OpDesc.od
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cpu/full_cpu/PipeTrace.od
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cpu/sampling_cpu/SamplingCPU.od
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cpu/simple_cpu/SimpleCPU.od
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cpu/BaseCPU.od
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cpu/IntrControl.od
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mem/bus/Bus.od
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mem/bus/BusBridge.od
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mem/cache/coherence/CoherenceProtocol.od
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mem/cache/tags/repl/GenRepl.od
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mem/cache/tags/repl/Repl.od
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mem/cache/BaseCache.od
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mem/functional_mem/FunctionalMemory.od
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mem/functional_mem/MainMemory.od
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mem/functional_mem/MemoryController.od
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mem/functional_mem/PhysicalMemory.od
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mem/timing_mem/BaseMemory.od
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mem/BaseHier.od
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mem/BaseMem.od
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mem/HierParams.od
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''')
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# MySql sources
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mysql_sources = Split('''
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base/mysql.cc
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base/stats/mysql.cc
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''')
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# Full-system sources
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full_system_sources = Split('''
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arch/alpha/alpha_memory.cc
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arch/alpha/arguments.cc
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arch/alpha/ev5.cc
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arch/alpha/osfpal.cc
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arch/alpha/pseudo_inst.cc
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arch/alpha/vtophys.cc
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base/inet.cc
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base/remote_gdb.cc
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cpu/intr_control.cc
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dev/alpha_console.cc
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dev/baddev.cc
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dev/simconsole.cc
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dev/disk_image.cc
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dev/dma.cc
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dev/etherbus.cc
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dev/etherdump.cc
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dev/etherint.cc
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dev/etherlink.cc
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dev/etherpkt.cc
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dev/ethertap.cc
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dev/ide_ctrl.cc
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dev/ide_disk.cc
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dev/io_device.cc
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dev/ns_gige.cc
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dev/etherdev.cc
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dev/pciconfigall.cc
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dev/pcidev.cc
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dev/scsi.cc
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dev/scsi_ctrl.cc
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dev/scsi_disk.cc
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dev/scsi_none.cc
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dev/simple_disk.cc
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dev/tlaser_clock.cc
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dev/tlaser_ipi.cc
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dev/tlaser_mbox.cc
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dev/tlaser_mc146818.cc
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dev/tlaser_node.cc
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dev/tlaser_pcia.cc
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dev/tlaser_pcidev.cc
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dev/tlaser_serial.cc
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dev/turbolaser.cc
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dev/tsunami.cc
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dev/tsunami_cchip.cc
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dev/tsunami_fake.cc
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dev/tsunami_io.cc
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dev/tsunami_pchip.cc
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dev/uart.cc
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kern/kernel_stats.cc
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kern/system_events.cc
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kern/linux/linux_events.cc
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kern/linux/linux_syscalls.cc
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kern/linux/linux_system.cc
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kern/linux/printk.cc
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kern/tru64/dump_mbuf.cc
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kern/tru64/printf.cc
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kern/tru64/tru64_events.cc
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kern/tru64/tru64_syscalls.cc
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kern/tru64/tru64_system.cc
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mem/functional_mem/memory_control.cc
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mem/functional_mem/physical_memory.cc
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dev/platform.cc
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sim/system.cc
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''')
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full_system_obj_desc_files = Split('''
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arch/alpha/AlphaDTB.od
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arch/alpha/AlphaITB.od
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arch/alpha/AlphaTLB.od
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dev/AlphaConsole.od
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dev/ConsoleListener.od
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dev/CowDiskImage.od
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dev/DiskImage.od
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dev/DmaDevice.od
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dev/DmaEngine.od
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dev/EtherBus.od
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dev/EtherDev.od
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dev/EtherDevInt.od
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dev/EtherDump.od
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dev/EtherInt.od
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dev/EtherLink.od
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dev/EtherTap.od
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dev/PioDevice.od
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dev/RawDiskImage.od
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dev/ScsiController.od
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dev/ScsiDevice.od
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dev/ScsiDisk.od
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dev/SimConsole.od
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dev/SimpleDisk.od
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dev/TlaserClock.od
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dev/TlaserIpi.od
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dev/TlaserMBox.od
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dev/TlaserMC146818.od
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dev/TlaserNode.od
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dev/TlaserPciDev.od
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dev/TlaserPcia.od
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dev/TlaserSerial.od
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dev/TlaserUart.od
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dev/Turbolaser.od
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kern/tru64/Tru64System.od
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sim/System.od
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''')
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# Syscall emulation (non-full-system) sources
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syscall_emulation_sources = Split('''
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arch/alpha/alpha_common_syscall_emul.cc
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arch/alpha/alpha_linux_process.cc
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arch/alpha/alpha_tru64_process.cc
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cpu/memtest/memtest.cc
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cpu/trace/trace_cpu.cc
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eio/eio.cc
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eio/exolex.cc
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eio/libexo.cc
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sim/process.cc
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sim/syscall_emul.cc
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''')
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syscall_emulation_obj_desc_files = Split('''
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cpu/memtest/MemTest.od
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eio/EioProcess.od
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sim/LiveProcess.od
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sim/Process.od
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''')
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# Set up complete list of sources based on configuration.
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sources = base_sources
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obj_desc_files = base_obj_desc_files
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if env['FULL_SYSTEM']:
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sources += full_system_sources
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obj_desc_files += full_system_obj_desc_files
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else:
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sources += syscall_emulation_sources
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obj_desc_files += syscall_emulation_obj_desc_files
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if env['USE_MYSQL']:
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sources += mysql_sources
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###################################################
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#
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# Special build rules.
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#
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###################################################
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# base/traceflags.{cc,hh} are generated from base/traceflags.py.
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# $TARGET.base will expand to "<build-dir>/base/traceflags".
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env.Command(Split('base/traceflags.hh base/traceflags.cc'),
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'base/traceflags.py',
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'python $SOURCE $TARGET.base')
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# several files are generated from arch/$TARGET_ISA/isa_desc.
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env.Command(Split('''arch/alpha/decoder.cc
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arch/alpha/decoder.hh
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arch/alpha/alpha_full_cpu_exec.cc
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arch/alpha/fast_cpu_exec.cc
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arch/alpha/simple_cpu_exec.cc
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arch/alpha/full_cpu_exec.cc'''),
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Split('''arch/alpha/isa_desc
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arch/isa_parser.py'''),
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'$SRCDIR/arch/isa_parser.py $SOURCE $TARGET.dir arch/alpha')
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# 'targetarch' is a symlink to arch/$TARGET_ISA.
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def link_targetarch(target, source, env):
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link_target = str(target[0])
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link_source = env.subst('$SRCDIR/arch/$TARGET_ISA')
|
|
if not os.path.isdir(link_target):
|
|
print "symlinking", link_source, "to", link_target
|
|
try:
|
|
os.symlink(link_source, link_target)
|
|
except OSError, desc:
|
|
print "Error creating symlink %s: %s" % (link_target, desc)
|
|
sys.exit(-1)
|
|
|
|
# Tell SCons to use the link_targetarch function to make 'targetarch'
|
|
env.Command('targetarch', None, link_targetarch)
|
|
|
|
|
|
# libelf build is described in its own SConscript file.
|
|
# SConscript-local is the per-config build, which just copies some
|
|
# header files into a place where they can be found.
|
|
SConscript('libelf/SConscript-local', exports = 'env', duplicate=0)
|
|
|
|
SConscript('sim/pyconfig/SConscript', exports = ['env', 'obj_desc_files'],
|
|
duplicate=0)
|
|
|
|
|
|
# This function adds the specified sources to the given build
|
|
# environment, and returns a list of all the corresponding SCons
|
|
# Object nodes (including an extra one for date.cc). We explicitly
|
|
# add the Object nodes so we can set up special dependencies for
|
|
# targetarch and date.cc.
|
|
def make_objs(sources, env):
|
|
objs = [env.Object(s) for s in sources]
|
|
# make all objects depend on the targetarch link so it gets made first.
|
|
env.Depends(objs, 'targetarch')
|
|
# make date.cc depend on all other objects so it always gets
|
|
# recompiled whenever anything else does
|
|
date_obj = env.Object('base/date.cc')
|
|
env.Depends(date_obj, objs)
|
|
objs.append(date_obj)
|
|
return objs
|
|
|
|
###################################################
|
|
#
|
|
# Define binaries. Each different build type (debug, opt, etc.) gets
|
|
# a slightly different build environment.
|
|
#
|
|
###################################################
|
|
|
|
# Include file paths are rooted in this directory. SCons will
|
|
# automatically expand '.' to refer to both the source directory and
|
|
# the corresponding build directory to pick up generated include
|
|
# files.
|
|
env.Append(CPPPATH='.')
|
|
|
|
# Debug binary
|
|
debug = env.Copy(OBJSUFFIX='.do')
|
|
debug.Append(CCFLAGS=Split('-g -gstabs+ -O0 -lefence'))
|
|
debug.Append(CPPDEFINES='DEBUG')
|
|
debug.Program(target = 'm5.debug', source = make_objs(sources, debug))
|
|
|
|
# Optimized binary
|
|
opt = env.Copy()
|
|
opt.Append(CCFLAGS=Split('-g -O5'))
|
|
opt.Program(target = 'm5.opt', source = make_objs(sources, opt))
|
|
|
|
# "Fast" binary
|
|
fast = env.Copy(OBJSUFFIX='.fo')
|
|
fast.Append(CCFLAGS=Split('-O5'))
|
|
fast.Append(CPPDEFINES='NDEBUG')
|
|
fast.Program(target = 'm5.fast.unstripped', source = make_objs(sources, fast))
|
|
fast.Command(target = 'm5.fast', source = 'm5.fast.unstripped',
|
|
action = 'strip $SOURCE -o $TARGET')
|
|
|
|
# Profiled binary
|
|
prof = env.Copy(OBJSUFFIX='.po')
|
|
prof.Append(CCFLAGS=Split('-O5 -g -pg'), LINKFLAGS='-pg')
|
|
prof.Program(target = 'm5.prof', source = make_objs(sources, prof))
|