2f5262eb67
Continue along the same line as the recent patch that made the Ruby-related config scripts Python packages and make also the configs/common directory a package. All affected config scripts are updated (hopefully). Note that this change makes it apparent that the current organisation and naming of the config directory and its subdirectories is rather chaotic. We mix scripts that are directly invoked with scripts that merely contain convenience functions. While it is not addressed in this patch we should follow up with a re-organisation of the config structure, and renaming of some of the packages.
350 lines
15 KiB
Python
350 lines
15 KiB
Python
#
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# Copyright (c) 2015 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# For use for simulation and test purposes only
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its contributors
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# may be used to endorse or promote products derived from this software
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# without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Brad Beckmann
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#
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys, math, glob
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m5.util.addToPath('../configs/')
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from ruby import Ruby
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from common import Options
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from common import GPUTLBOptions, GPUTLBConfig
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########################## Script Options ########################
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def setOption(parser, opt_str, value = 1):
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# check to make sure the option actually exists
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if not parser.has_option(opt_str):
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raise Exception("cannot find %s in list of possible options" % opt_str)
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opt = parser.get_option(opt_str)
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# set the value
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exec("parser.values.%s = %s" % (opt.dest, value))
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def getOption(parser, opt_str):
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# check to make sure the option actually exists
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if not parser.has_option(opt_str):
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raise Exception("cannot find %s in list of possible options" % opt_str)
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opt = parser.get_option(opt_str)
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# get the value
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exec("return_value = parser.values.%s" % opt.dest)
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return return_value
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def run_test(root):
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"""gpu test requires a specialized run_test implementation to set up the
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mmio space."""
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# instantiate configuration
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m5.instantiate()
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# Now that the system has been constructed, setup the mmio space
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root.system.cpu[0].workload[0].map(0x10000000, 0x200000000, 4096)
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# simulate until program terminates
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exit_event = m5.simulate(maxtick)
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addSEOptions(parser)
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parser.add_option("-k", "--kernel-files",
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help="file(s) containing GPU kernel code (colon separated)")
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parser.add_option("-u", "--num-compute-units", type="int", default=2,
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help="number of GPU compute units"),
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parser.add_option("--num-cp", type="int", default=0,
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help="Number of GPU Command Processors (CP)")
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parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \
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"per CU")
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parser.add_option("--cu-per-sqc", type="int", default=4, help="number of CUs" \
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"sharing an SQC (icache, and thus icache TLB)")
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parser.add_option("--wf-size", type="int", default=64,
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help="Wavefront size(in workitems)")
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parser.add_option("--wfs-per-simd", type="int", default=8, help="Number of " \
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"WF slots per SIMD")
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parser.add_option("--sp-bypass-path-length", type="int", default=4, \
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help="Number of stages of bypass path in vector ALU for Single "\
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"Precision ops")
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parser.add_option("--dp-bypass-path-length", type="int", default=4, \
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help="Number of stages of bypass path in vector ALU for Double "\
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"Precision ops")
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parser.add_option("--issue-period", type="int", default=4, \
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help="Number of cycles per vector instruction issue period")
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parser.add_option("--glbmem-wr-bus-width", type="int", default=32, \
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help="VGPR to Coalescer (Global Memory) data bus width in bytes")
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parser.add_option("--glbmem-rd-bus-width", type="int", default=32, \
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help="Coalescer to VGPR (Global Memory) data bus width in bytes")
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parser.add_option("--shr-mem-pipes-per-cu", type="int", default=1, \
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help="Number of Shared Memory pipelines per CU")
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parser.add_option("--glb-mem-pipes-per-cu", type="int", default=1, \
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help="Number of Global Memory pipelines per CU")
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parser.add_option("--vreg-file-size", type="int", default=2048,
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help="number of physical vector registers per SIMD")
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parser.add_option("--bw-scalor", type="int", default=0,
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help="bandwidth scalor for scalability analysis")
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parser.add_option("--CPUClock", type="string", default="2GHz",
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help="CPU clock")
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parser.add_option("--GPUClock", type="string", default="1GHz",
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help="GPU clock")
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parser.add_option("--cpu-voltage", action="store", type="string",
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default='1.0V',
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help = """CPU voltage domain""")
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parser.add_option("--gpu-voltage", action="store", type="string",
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default='1.0V',
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help = """CPU voltage domain""")
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parser.add_option("--CUExecPolicy", type="string", default="OLDEST-FIRST",
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help="WF exec policy (OLDEST-FIRST, ROUND-ROBIN)")
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parser.add_option("--xact-cas-mode", action="store_true",
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help="enable load_compare mode (transactional CAS)")
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parser.add_option("--SegFaultDebug",action="store_true",
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help="checks for GPU seg fault before TLB access")
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parser.add_option("--LocalMemBarrier",action="store_true",
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help="Barrier does not wait for writethroughs to complete")
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parser.add_option("--countPages", action="store_true",
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help="Count Page Accesses and output in per-CU output files")
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parser.add_option("--TLB-prefetch", type="int", help = "prefetch depth for"\
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"TLBs")
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parser.add_option("--pf-type", type="string", help="type of prefetch: "\
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"PF_CU, PF_WF, PF_PHASE, PF_STRIDE")
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parser.add_option("--pf-stride", type="int", help="set prefetch stride")
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parser.add_option("--numLdsBanks", type="int", default=32,
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help="number of physical banks per LDS module")
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parser.add_option("--ldsBankConflictPenalty", type="int", default=1,
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help="number of cycles per LDS bank conflict")
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# Add the ruby specific and protocol specific options
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Ruby.define_options(parser)
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GPUTLBOptions.tlb_options(parser)
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(options, args) = parser.parse_args()
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# The GPU cache coherence protocols only work with the backing store
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setOption(parser, "--access-backing-store")
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# Currently, the sqc (I-Cache of GPU) is shared by
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# multiple compute units(CUs). The protocol works just fine
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# even if sqc is not shared. Overriding this option here
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# so that the user need not explicitly set this (assuming
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# sharing sqc is the common usage)
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n_cu = options.num_compute_units
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num_sqc = int(math.ceil(float(n_cu) / options.cu_per_sqc))
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options.num_sqc = num_sqc # pass this to Ruby
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########################## Creating the GPU system ########################
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# shader is the GPU
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shader = Shader(n_wf = options.wfs_per_simd,
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clk_domain = SrcClockDomain(
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clock = options.GPUClock,
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voltage_domain = VoltageDomain(
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voltage = options.gpu_voltage)),
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timing = True)
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# GPU_RfO(Read For Ownership) implements SC/TSO memory model.
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# Other GPU protocols implement release consistency at GPU side.
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# So, all GPU protocols other than GPU_RfO should make their writes
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# visible to the global memory and should read from global memory
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# during kernal boundary. The pipeline initiates(or do not initiate)
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# the acquire/release operation depending on this impl_kern_boundary_sync
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# flag. This flag=true means pipeline initiates a acquire/release operation
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# at kernel boundary.
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if buildEnv['PROTOCOL'] == 'GPU_RfO':
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shader.impl_kern_boundary_sync = False
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else:
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shader.impl_kern_boundary_sync = True
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# Switching off per-lane TLB by default
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per_lane = False
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if options.TLB_config == "perLane":
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per_lane = True
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# List of compute units; one GPU can have multiple compute units
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compute_units = []
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for i in xrange(n_cu):
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compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane,
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num_SIMDs = options.simds_per_cu,
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wfSize = options.wf_size,
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spbypass_pipe_length = \
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options.sp_bypass_path_length,
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dpbypass_pipe_length = \
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options.dp_bypass_path_length,
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issue_period = options.issue_period,
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coalescer_to_vrf_bus_width = \
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options.glbmem_rd_bus_width,
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vrf_to_coalescer_bus_width = \
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options.glbmem_wr_bus_width,
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num_global_mem_pipes = \
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options.glb_mem_pipes_per_cu,
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num_shared_mem_pipes = \
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options.shr_mem_pipes_per_cu,
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n_wf = options.wfs_per_simd,
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execPolicy = options.CUExecPolicy,
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xactCasMode = options.xact_cas_mode,
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debugSegFault = options.SegFaultDebug,
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functionalTLB = True,
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localMemBarrier = options.LocalMemBarrier,
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countPages = options.countPages,
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localDataStore = \
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LdsState(banks = options.numLdsBanks,
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bankConflictPenalty = \
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options.ldsBankConflictPenalty)))
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wavefronts = []
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vrfs = []
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for j in xrange(options.simds_per_cu):
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for k in xrange(shader.n_wf):
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wavefronts.append(Wavefront(simdId = j, wf_slot_id = k))
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vrfs.append(VectorRegisterFile(simd_id=j,
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num_regs_per_simd=options.vreg_file_size))
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compute_units[-1].wavefronts = wavefronts
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compute_units[-1].vector_register_file = vrfs
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if options.TLB_prefetch:
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compute_units[-1].prefetch_depth = options.TLB_prefetch
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compute_units[-1].prefetch_prev_type = options.pf_type
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# attach the LDS and the CU to the bus (actually a Bridge)
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compute_units[-1].ldsPort = compute_units[-1].ldsBus.slave
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compute_units[-1].ldsBus.master = compute_units[-1].localDataStore.cuPort
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# Attach compute units to GPU
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shader.CUs = compute_units
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# this is a uniprocessor only test, thus the shader is the second index in the
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# list of "system.cpus"
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options.num_cpus = 1
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shader_idx = 1
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cpu = TimingSimpleCPU(cpu_id=0)
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########################## Creating the GPU dispatcher ########################
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# Dispatcher dispatches work from host CPU to GPU
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host_cpu = cpu
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dispatcher = GpuDispatcher()
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# Currently does not test for command processors
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cpu_list = [cpu] + [shader] + [dispatcher]
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system = System(cpu = cpu_list,
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mem_ranges = [AddrRange(options.mem_size)],
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mem_mode = 'timing')
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# Dummy voltage domain for all our clock domains
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system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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system.clk_domain = SrcClockDomain(clock = '1GHz',
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voltage_domain = system.voltage_domain)
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# Create a seperate clock domain for components that should run at
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# CPUs frequency
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system.cpu[0].clk_domain = SrcClockDomain(clock = '2GHz',
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voltage_domain = \
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system.voltage_domain)
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# configure the TLB hierarchy
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GPUTLBConfig.config_tlb_hierarchy(options, system, shader_idx)
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# create Ruby system
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system.piobus = IOXBar(width=32, response_latency=0,
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frontend_latency=0, forward_latency=0)
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Ruby.create_system(options, None, system)
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# Create a separate clock for Ruby
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system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = system.voltage_domain)
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# create the interrupt controller
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cpu.createInterruptController()
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#
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# Tie the cpu cache ports to the ruby cpu ports and
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# physmem, respectively
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#
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cpu.connectAllPorts(system.ruby._cpu_ports[0])
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system.ruby._cpu_ports[0].mem_master_port = system.piobus.slave
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# attach CU ports to Ruby
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# Because of the peculiarities of the CP core, you may have 1 CPU but 2
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# sequencers and thus 2 _cpu_ports created. Your GPUs shouldn't be
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# hooked up until after the CP. To make this script generic, figure out
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# the index as below, but note that this assumes there is one sequencer
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# per compute unit and one sequencer per SQC for the math to work out
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# correctly.
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gpu_port_idx = len(system.ruby._cpu_ports) \
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- options.num_compute_units - options.num_sqc
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gpu_port_idx = gpu_port_idx - options.num_cp * 2
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wavefront_size = options.wf_size
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for i in xrange(n_cu):
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# The pipeline issues wavefront_size number of uncoalesced requests
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# in one GPU issue cycle. Hence wavefront_size mem ports.
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for j in xrange(wavefront_size):
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system.cpu[shader_idx].CUs[i].memory_port[j] = \
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system.ruby._cpu_ports[gpu_port_idx].slave[j]
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gpu_port_idx += 1
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for i in xrange(n_cu):
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if i > 0 and not i % options.cu_per_sqc:
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gpu_port_idx += 1
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system.cpu[shader_idx].CUs[i].sqc_port = \
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system.ruby._cpu_ports[gpu_port_idx].slave
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gpu_port_idx = gpu_port_idx + 1
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# Current regression tests do not support the command processor
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assert(options.num_cp == 0)
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# connect dispatcher to the system.piobus
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dispatcher.pio = system.piobus.master
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dispatcher.dma = system.piobus.slave
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################# Connect the CPU and GPU via GPU Dispatcher ###################
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# CPU rings the GPU doorbell to notify a pending task
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# using this interface.
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# And GPU uses this interface to notify the CPU of task completion
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# The communcation happens through emulated driver.
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# Note this implicit setting of the cpu_pointer, shader_pointer and tlb array
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# parameters must be after the explicit setting of the System cpu list
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shader.cpu_pointer = host_cpu
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dispatcher.cpu = host_cpu
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dispatcher.shader_pointer = shader
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# -----------------------
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# run simulation
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# -----------------------
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root = Root(full_system = False, system = system)
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m5.ticks.setGlobalFrequency('1THz')
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root.system.mem_mode = 'timing'
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