2f316082e4
arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/full_cpu/op_class.hh: cpu/full_cpu/smt.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: cpu/pc_event.cc: cpu/pc_event.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.cc: cpu/static_inst.hh: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/platform.cc: dev/platform.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunami_uart.hh: dev/tsunamireg.h: docs/stl.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: sim/universe.cc: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/m5/m5.c: util/m5/m5op.h: util/tap/tap.cc: Updated Copyright dev/console.cc: dev/console.hh: This code isn't ours, and shouldn't have our copyright --HG-- extra : convert_revision : 598f2e5eab5d5d3de2c1e862b389086e3212f7c4
204 lines
4.3 KiB
C++
204 lines
4.3 KiB
C++
/*
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* Copyright (c) 2001, 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __INTMATH_HH__
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#define __INTMATH_HH__
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#include <assert.h>
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#include "sim/host.hh"
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// Returns the prime number one less than n.
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int PrevPrime(int n);
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// Determine if a number is prime
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template <class T>
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inline bool
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IsPrime(T n)
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{
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T i;
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if (n == 2 || n == 3)
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return true;
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// Don't try every odd number to prove if it is a prime.
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// Toggle between every 2nd and 4th number.
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// (This is because every 6th odd number is divisible by 3.)
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for (i = 5; i*i <= n; i += 6) {
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if (((n % i) == 0 ) || ((n % (i + 2)) == 0) ) {
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return false;
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}
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}
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return true;
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}
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template <class T>
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inline T
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LeastSigBit(T n)
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{
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return n & ~(n - 1);
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}
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template <class T>
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inline bool
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IsPowerOf2(T n)
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{
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return n != 0 && LeastSigBit(n) == n;
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}
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inline int
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FloorLog2(uint32_t x)
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{
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assert(x > 0);
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int y = 0;
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if (x & 0xffff0000) { y += 16; x >>= 16; }
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if (x & 0x0000ff00) { y += 8; x >>= 8; }
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if (x & 0x000000f0) { y += 4; x >>= 4; }
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if (x & 0x0000000c) { y += 2; x >>= 2; }
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if (x & 0x00000002) { y += 1; }
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return y;
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}
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inline int
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FloorLog2(uint64_t x)
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{
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assert(x > 0);
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int y = 0;
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if (x & ULL(0xffffffff00000000)) { y += 32; x >>= 32; }
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if (x & ULL(0x00000000ffff0000)) { y += 16; x >>= 16; }
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if (x & ULL(0x000000000000ff00)) { y += 8; x >>= 8; }
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if (x & ULL(0x00000000000000f0)) { y += 4; x >>= 4; }
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if (x & ULL(0x000000000000000c)) { y += 2; x >>= 2; }
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if (x & ULL(0x0000000000000002)) { y += 1; }
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return y;
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}
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inline int
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FloorLog2(int32_t x)
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{
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assert(x > 0);
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return FloorLog2((uint32_t)x);
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}
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inline int
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FloorLog2(int64_t x)
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{
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assert(x > 0);
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return FloorLog2((uint64_t)x);
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}
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template <class T>
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inline int
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CeilLog2(T n)
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{
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if (n == 1)
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return 0;
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return FloorLog2(n - (T)1) + 1;
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}
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template <class T>
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inline T
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FloorPow2(T n)
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{
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return (T)1 << FloorLog2(n);
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}
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template <class T>
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inline T
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CeilPow2(T n)
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{
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return (T)1 << CeilLog2(n);
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}
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template <class T>
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inline T
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DivCeil(T a, T b)
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{
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return (a + b - 1) / b;
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}
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template <class T>
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inline T
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RoundUp(T val, T align)
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{
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T mask = align - 1;
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return (val + mask) & ~mask;
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}
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template <class T>
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inline T
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RoundDown(T val, T align)
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{
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T mask = align - 1;
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return val & ~mask;
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}
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inline bool
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IsHex(char c)
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{
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return c >= '0' && c <= '9' ||
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c >= 'A' && c <= 'F' ||
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c >= 'a' && c <= 'f';
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}
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inline bool
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IsOct(char c)
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{
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return c >= '0' && c <= '7';
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}
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inline bool
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IsDec(char c)
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{
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return c >= '0' && c <= '9';
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}
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inline int
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Hex2Int(char c)
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{
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if (c >= '0' && c <= '9')
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return (c - '0');
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if (c >= 'A' && c <= 'F')
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return (c - 'A') + 10;
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if (c >= 'a' && c <= 'f')
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return (c - 'a') + 10;
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return 0;
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}
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#endif // __INTMATH_HH__
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