2f145ac54a
Kinda port DRAM to new memory system. The code is *really* ugly (not my fault) and right now something about the stats it uses
causes a simulator segfault.
src/SConscript:
Add dram.cc to sconscript
src/mem/physical.cc:
src/mem/physical.hh:
Add params struct to physical memory, use params, make latency function be virtual
src/python/m5/objects/PhysicalMemory.py:
Add DRAMMemory python class
--HG--
extra : convert_revision : 5bd9f2e071c62da89e8efa46fa016f342c01535d
173 lines
5.1 KiB
C++
173 lines
5.1 KiB
C++
/*
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* Copyright (c) 2003-2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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* Ali Saidi
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*/
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/**
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* @file
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* Derrive a class from PhysicalMemory that support DRAM like timing access.
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*/
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#ifndef __MEM_DRAM_HH__
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#define __MEM_DRAM_HH__
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#include "base/statistics.hh"
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#include "mem/physical.hh"
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class DRAMMemory : public PhysicalMemory
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{
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protected:
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/* added for dram support */
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const int cpu_ratio; // ratio between CPU speed and memory bus speed
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const int bus_width; // memory access bus width (in bytes)
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/* memory access latency (<first_chunk> <inter_chunk>) */
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const std::string mem_type;
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const std::string mem_actpolicy;
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const std::string memctrladdr_type;
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const int act_lat;
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const int cas_lat;
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const int war_lat;
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const int pre_lat;
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const int dpl_lat;
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const int trc_lat;
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const int num_banks;
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const int num_cpus;
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int bank_size;
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int num_rows;
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int *active_row;
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int last_bank;
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int last_row;
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Tick *busy_until;
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int last_dev;
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bool lastCmdIsRead;
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int precharge;
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/* memory access statistics */
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int same_row_read_access;
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int srr_after_read;
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int srr_after_write;
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int same_row_write_access;
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int srw_after_read;
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int srw_after_write;
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int same_bank_read_access;
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int sbr_after_read;
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int sbr_after_write;
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int same_bank_write_access;
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int sbw_after_read;
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int sbw_after_write;
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int other_bank_read_access_hit;
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int obr_after_read_hit;
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int obr_after_write_hit;
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int other_bank_write_access_hit;
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int obw_after_read_hit;
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int obw_after_write_hit;
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// DR
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// int other_bank_read_access_miss;
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int obr_after_read_miss;
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int obr_after_write_miss;
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// DR
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// int other_bank_write_access_miss;
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int obw_after_read_miss;
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int obw_after_write_miss;
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int total_access;
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int adjacent_access;
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int adjacent_read;
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int adjacent_write;
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int command_overlapping;
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int best_case;
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int in_between_case;
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int worst_case;
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int full_overlapping;
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int partial_overlapping;
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int mem_access_details;
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int memctrlpipe_enable;
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Tick time_last_access;
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Stats::Vector<> accesses;
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Stats::Vector<> bytesRequested;
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Stats::Vector<> bytesSent;
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Stats::Vector<> compressedAccesses;
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Stats::Vector<> cycles_nCKE;
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Stats::Vector<> cycles_all_precharge_CKE;
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Stats::Vector<> cycles_all_precharge_nCKE;
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Stats::Vector<> cycles_bank_active_nCKE;
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Stats::Vector<> cycles_avg_ACT;
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Stats::Vector<> cycles_read_out;
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Stats::Vector<> cycles_write_in;
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Stats::Vector<> cycles_between_misses;
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Stats::Vector<> other_bank_read_access_miss;
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Stats::Vector<> other_bank_write_access_miss;
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Stats::Scalar<> total_latency;
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Stats::Scalar<> total_icache_req;
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Stats::Scalar<> total_arb_latency;
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Stats::Formula avg_latency;
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Stats::Formula avg_arb_latency;
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Stats::Vector2d<> bank_access_profile;
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protected:
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Tick calculateLatency(Packet *pkt);
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int prechargeBanksAround(int bank);
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public:
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struct Params : public PhysicalMemory::Params
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{
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/* additional params for dram protocol*/
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int cpu_ratio;
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int bus_width;
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std::string mem_type; /* DRDRAM, SDRAM */
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std::string mem_actpolicy; /* closed, open */
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std::string memctrladdr_type; /* interleaved, anythingelse */
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int act_lat;
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int cas_lat;
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int war_lat;
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int pre_lat;
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int dpl_lat;
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int trc_lat;
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int num_banks;
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int num_cpus;
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};
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virtual void regStats();
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DRAMMemory(Params *p);
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};
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#endif// __MEM_DRAM_HH__
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