be4aa2b6ba
Newer linux kernels and distros exercise more functionality in the IDE device than previously, exposing 2 races. The first race is the handling of aborted DMA commands would immediately report the device is ready back to the kernel and cause already in flight commands to assert the simulator when they returned and discovered an inconsitent device state. The second race was due to the Status register not being handled correctly, the interrupt status bit would get stuck at 1 and the driver eventually views this as a bad state and logs the condition to the terminal. This patch fixes these two conditions by making the device handle aborted commands gracefully and properly handles clearing the interrupt status bit in the Status register.
635 lines
20 KiB
C++
635 lines
20 KiB
C++
/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andrew Schultz
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* Ali Saidi
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* Miguel Serrano
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*/
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#include <string>
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#include "cpu/intr_control.hh"
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#include "debug/IdeCtrl.hh"
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#include "dev/ide_ctrl.hh"
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#include "dev/ide_disk.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "params/IdeController.hh"
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#include "sim/byteswap.hh"
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// clang complains about std::set being overloaded with Packet::set if
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// we open up the entire namespace std
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using std::string;
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// Bus master IDE registers
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enum BMIRegOffset {
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BMICommand = 0x0,
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BMIStatus = 0x2,
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BMIDescTablePtr = 0x4
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};
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// PCI config space registers
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enum ConfRegOffset {
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PrimaryTiming = 0x40,
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SecondaryTiming = 0x42,
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DeviceTiming = 0x44,
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UDMAControl = 0x48,
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UDMATiming = 0x4A,
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IDEConfig = 0x54
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};
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static const uint16_t timeRegWithDecodeEn = 0x8000;
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IdeController::Channel::Channel(
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string newName, Addr _cmdSize, Addr _ctrlSize) :
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_name(newName),
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cmdAddr(0), cmdSize(_cmdSize), ctrlAddr(0), ctrlSize(_ctrlSize),
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master(NULL), slave(NULL), selected(NULL)
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{
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memset(&bmiRegs, 0, sizeof(bmiRegs));
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bmiRegs.status.dmaCap0 = 1;
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bmiRegs.status.dmaCap1 = 1;
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}
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IdeController::Channel::~Channel()
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{
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}
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IdeController::IdeController(Params *p)
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: PciDevice(p), primary(name() + ".primary", BARSize[0], BARSize[1]),
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secondary(name() + ".secondary", BARSize[2], BARSize[3]),
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bmiAddr(0), bmiSize(BARSize[4]),
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primaryTiming(htole(timeRegWithDecodeEn)),
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secondaryTiming(htole(timeRegWithDecodeEn)),
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deviceTiming(0), udmaControl(0), udmaTiming(0), ideConfig(0),
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ioEnabled(false), bmEnabled(false),
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ioShift(p->io_shift), ctrlOffset(p->ctrl_offset)
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{
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if (params()->disks.size() > 3)
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panic("IDE controllers support a maximum of 4 devices attached!\n");
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// Assign the disks to channels
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int numDisks = params()->disks.size();
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if (numDisks > 0)
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primary.master = params()->disks[0];
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if (numDisks > 1)
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primary.slave = params()->disks[1];
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if (numDisks > 2)
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secondary.master = params()->disks[2];
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if (numDisks > 3)
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secondary.slave = params()->disks[3];
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for (int i = 0; i < params()->disks.size(); i++) {
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params()->disks[i]->setController(this);
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}
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primary.select(false);
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secondary.select(false);
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if ((BARAddrs[0] & ~BAR_IO_MASK) && (!legacyIO[0] || ioShift)) {
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primary.cmdAddr = BARAddrs[0]; primary.cmdSize = BARSize[0];
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primary.ctrlAddr = BARAddrs[1]; primary.ctrlSize = BARSize[1];
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}
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if ((BARAddrs[2] & ~BAR_IO_MASK) && (!legacyIO[2] || ioShift)) {
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secondary.cmdAddr = BARAddrs[2]; secondary.cmdSize = BARSize[2];
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secondary.ctrlAddr = BARAddrs[3]; secondary.ctrlSize = BARSize[3];
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}
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ioEnabled = (config.command & htole(PCI_CMD_IOSE));
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bmEnabled = (config.command & htole(PCI_CMD_BME));
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}
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bool
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IdeController::isDiskSelected(IdeDisk *diskPtr)
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{
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return (primary.selected == diskPtr || secondary.selected == diskPtr);
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}
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void
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IdeController::intrPost()
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{
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primary.bmiRegs.status.intStatus = 1;
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PciDevice::intrPost();
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}
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void
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IdeController::setDmaComplete(IdeDisk *disk)
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{
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Channel *channel;
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if (disk == primary.master || disk == primary.slave) {
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channel = &primary;
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} else if (disk == secondary.master || disk == secondary.slave) {
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channel = &secondary;
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} else {
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panic("Unable to find disk based on pointer %#x\n", disk);
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}
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channel->bmiRegs.command.startStop = 0;
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channel->bmiRegs.status.active = 0;
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channel->bmiRegs.status.intStatus = 1;
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}
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Tick
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IdeController::readConfig(PacketPtr pkt)
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{
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int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
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if (offset < PCI_DEVICE_SPECIFIC) {
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return PciDevice::readConfig(pkt);
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}
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pkt->allocate();
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switch (pkt->getSize()) {
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case sizeof(uint8_t):
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switch (offset) {
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case DeviceTiming:
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pkt->set<uint8_t>(deviceTiming);
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break;
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case UDMAControl:
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pkt->set<uint8_t>(udmaControl);
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break;
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case PrimaryTiming + 1:
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pkt->set<uint8_t>(bits(htole(primaryTiming), 15, 8));
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break;
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case SecondaryTiming + 1:
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pkt->set<uint8_t>(bits(htole(secondaryTiming), 15, 8));
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break;
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case IDEConfig:
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pkt->set<uint8_t>(bits(htole(ideConfig), 7, 0));
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break;
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case IDEConfig + 1:
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pkt->set<uint8_t>(bits(htole(ideConfig), 15, 8));
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break;
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default:
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panic("Invalid PCI configuration read for size 1 at offset: %#x!\n",
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offset);
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}
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DPRINTF(IdeCtrl, "PCI read offset: %#x size: 1 data: %#x\n", offset,
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(uint32_t)pkt->get<uint8_t>());
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break;
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case sizeof(uint16_t):
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switch (offset) {
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case PrimaryTiming:
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pkt->set<uint16_t>(primaryTiming);
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break;
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case SecondaryTiming:
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pkt->set<uint16_t>(secondaryTiming);
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break;
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case UDMATiming:
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pkt->set<uint16_t>(udmaTiming);
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break;
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case IDEConfig:
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pkt->set<uint16_t>(ideConfig);
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break;
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default:
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panic("Invalid PCI configuration read for size 2 offset: %#x!\n",
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offset);
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}
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DPRINTF(IdeCtrl, "PCI read offset: %#x size: 2 data: %#x\n", offset,
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(uint32_t)pkt->get<uint16_t>());
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break;
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case sizeof(uint32_t):
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if (offset == IDEConfig)
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pkt->set<uint32_t>(ideConfig);
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else
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panic("No 32bit reads implemented for this device.");
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DPRINTF(IdeCtrl, "PCI read offset: %#x size: 4 data: %#x\n", offset,
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(uint32_t)pkt->get<uint32_t>());
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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pkt->makeAtomicResponse();
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return configDelay;
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}
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Tick
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IdeController::writeConfig(PacketPtr pkt)
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{
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int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
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if (offset < PCI_DEVICE_SPECIFIC) {
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PciDevice::writeConfig(pkt);
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} else {
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switch (pkt->getSize()) {
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case sizeof(uint8_t):
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switch (offset) {
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case DeviceTiming:
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deviceTiming = pkt->get<uint8_t>();
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break;
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case UDMAControl:
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udmaControl = pkt->get<uint8_t>();
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break;
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case IDEConfig:
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replaceBits(ideConfig, 7, 0, pkt->get<uint8_t>());
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break;
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case IDEConfig + 1:
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replaceBits(ideConfig, 15, 8, pkt->get<uint8_t>());
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break;
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default:
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panic("Invalid PCI configuration write "
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"for size 1 offset: %#x!\n", offset);
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}
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DPRINTF(IdeCtrl, "PCI write offset: %#x size: 1 data: %#x\n",
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offset, (uint32_t)pkt->get<uint8_t>());
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break;
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case sizeof(uint16_t):
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switch (offset) {
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case PrimaryTiming:
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primaryTiming = pkt->get<uint16_t>();
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break;
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case SecondaryTiming:
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secondaryTiming = pkt->get<uint16_t>();
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break;
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case UDMATiming:
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udmaTiming = pkt->get<uint16_t>();
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break;
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case IDEConfig:
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ideConfig = pkt->get<uint16_t>();
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break;
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default:
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panic("Invalid PCI configuration write "
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"for size 2 offset: %#x!\n",
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offset);
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}
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DPRINTF(IdeCtrl, "PCI write offset: %#x size: 2 data: %#x\n",
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offset, (uint32_t)pkt->get<uint16_t>());
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break;
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case sizeof(uint32_t):
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if (offset == IDEConfig)
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ideConfig = pkt->get<uint32_t>();
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else
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panic("Write of unimplemented PCI config. register: %x\n", offset);
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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pkt->makeAtomicResponse();
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}
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/* Trap command register writes and enable IO/BM as appropriate as well as
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* BARs. */
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switch(offset) {
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case PCI0_BASE_ADDR0:
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if (BARAddrs[0] != 0)
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primary.cmdAddr = BARAddrs[0];
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break;
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case PCI0_BASE_ADDR1:
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if (BARAddrs[1] != 0)
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primary.ctrlAddr = BARAddrs[1];
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break;
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case PCI0_BASE_ADDR2:
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if (BARAddrs[2] != 0)
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secondary.cmdAddr = BARAddrs[2];
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break;
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case PCI0_BASE_ADDR3:
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if (BARAddrs[3] != 0)
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secondary.ctrlAddr = BARAddrs[3];
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break;
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case PCI0_BASE_ADDR4:
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if (BARAddrs[4] != 0)
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bmiAddr = BARAddrs[4];
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break;
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case PCI_COMMAND:
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DPRINTF(IdeCtrl, "Writing to PCI Command val: %#x\n", config.command);
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ioEnabled = (config.command & htole(PCI_CMD_IOSE));
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bmEnabled = (config.command & htole(PCI_CMD_BME));
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break;
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}
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return configDelay;
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}
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void
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IdeController::Channel::accessCommand(Addr offset,
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int size, uint8_t *data, bool read)
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{
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const Addr SelectOffset = 6;
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const uint8_t SelectDevBit = 0x10;
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if (!read && offset == SelectOffset)
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select(*data & SelectDevBit);
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if (selected == NULL) {
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assert(size == sizeof(uint8_t));
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*data = 0;
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} else if (read) {
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selected->readCommand(offset, size, data);
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} else {
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selected->writeCommand(offset, size, data);
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}
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}
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void
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IdeController::Channel::accessControl(Addr offset,
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int size, uint8_t *data, bool read)
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{
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if (selected == NULL) {
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assert(size == sizeof(uint8_t));
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*data = 0;
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} else if (read) {
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selected->readControl(offset, size, data);
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} else {
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selected->writeControl(offset, size, data);
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}
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}
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void
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IdeController::Channel::accessBMI(Addr offset,
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int size, uint8_t *data, bool read)
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{
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assert(offset + size <= sizeof(BMIRegs));
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if (read) {
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memcpy(data, (uint8_t *)&bmiRegs + offset, size);
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} else {
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switch (offset) {
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case BMICommand:
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{
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if (size != sizeof(uint8_t))
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panic("Invalid BMIC write size: %x\n", size);
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BMICommandReg oldVal = bmiRegs.command;
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BMICommandReg newVal = *data;
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// if a DMA transfer is in progress, R/W control cannot change
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if (oldVal.startStop && oldVal.rw != newVal.rw)
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oldVal.rw = newVal.rw;
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if (oldVal.startStop != newVal.startStop) {
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if (selected == NULL)
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panic("DMA start for disk which does not exist\n");
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if (oldVal.startStop) {
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DPRINTF(IdeCtrl, "Stopping DMA transfer\n");
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bmiRegs.status.active = 0;
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selected->abortDma();
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} else {
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DPRINTF(IdeCtrl, "Starting DMA transfer\n");
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bmiRegs.status.active = 1;
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selected->startDma(letoh(bmiRegs.bmidtp));
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}
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}
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bmiRegs.command = newVal;
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}
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break;
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case BMIStatus:
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{
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if (size != sizeof(uint8_t))
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panic("Invalid BMIS write size: %x\n", size);
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BMIStatusReg oldVal = bmiRegs.status;
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BMIStatusReg newVal = *data;
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// the BMIDEA bit is read only
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newVal.active = oldVal.active;
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// to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
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if ((oldVal.intStatus == 1) && (newVal.intStatus == 1)) {
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newVal.intStatus = 0; // clear the interrupt?
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} else {
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// Assigning two bitunion fields to each other does not
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// work as intended, so we need to use this temporary variable
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// to get around the bug.
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uint8_t tmp = oldVal.intStatus;
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newVal.intStatus = tmp;
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}
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if ((oldVal.dmaError == 1) && (newVal.dmaError == 1)) {
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newVal.dmaError = 0;
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} else {
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uint8_t tmp = oldVal.dmaError;
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newVal.dmaError = tmp;
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}
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bmiRegs.status = newVal;
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}
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break;
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case BMIDescTablePtr:
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if (size != sizeof(uint32_t))
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panic("Invalid BMIDTP write size: %x\n", size);
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bmiRegs.bmidtp = htole(*(uint32_t *)data & ~0x3);
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break;
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default:
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if (size != sizeof(uint8_t) && size != sizeof(uint16_t) &&
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size != sizeof(uint32_t))
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panic("IDE controller write of invalid write size: %x\n", size);
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memcpy((uint8_t *)&bmiRegs + offset, data, size);
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}
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}
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}
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void
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IdeController::dispatchAccess(PacketPtr pkt, bool read)
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{
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pkt->allocate();
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if (pkt->getSize() != 1 && pkt->getSize() != 2 && pkt->getSize() !=4)
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panic("Bad IDE read size: %d\n", pkt->getSize());
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if (!ioEnabled) {
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pkt->makeAtomicResponse();
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DPRINTF(IdeCtrl, "io not enabled\n");
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return;
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}
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Addr addr = pkt->getAddr();
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int size = pkt->getSize();
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uint8_t *dataPtr = pkt->getPtr<uint8_t>();
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if (addr >= primary.cmdAddr &&
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addr < (primary.cmdAddr + primary.cmdSize)) {
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addr -= primary.cmdAddr;
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// linux may have shifted the address by ioShift,
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// here we shift it back, similarly for ctrlOffset.
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addr >>= ioShift;
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primary.accessCommand(addr, size, dataPtr, read);
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} else if (addr >= primary.ctrlAddr &&
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addr < (primary.ctrlAddr + primary.ctrlSize)) {
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addr -= primary.ctrlAddr;
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addr += ctrlOffset;
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primary.accessControl(addr, size, dataPtr, read);
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} else if (addr >= secondary.cmdAddr &&
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addr < (secondary.cmdAddr + secondary.cmdSize)) {
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addr -= secondary.cmdAddr;
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secondary.accessCommand(addr, size, dataPtr, read);
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} else if (addr >= secondary.ctrlAddr &&
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addr < (secondary.ctrlAddr + secondary.ctrlSize)) {
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addr -= secondary.ctrlAddr;
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secondary.accessControl(addr, size, dataPtr, read);
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} else if (addr >= bmiAddr && addr < (bmiAddr + bmiSize)) {
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if (!read && !bmEnabled)
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return;
|
|
addr -= bmiAddr;
|
|
if (addr < sizeof(Channel::BMIRegs)) {
|
|
primary.accessBMI(addr, size, dataPtr, read);
|
|
} else {
|
|
addr -= sizeof(Channel::BMIRegs);
|
|
secondary.accessBMI(addr, size, dataPtr, read);
|
|
}
|
|
} else {
|
|
panic("IDE controller access to invalid address: %#x\n", addr);
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
uint32_t data;
|
|
if (pkt->getSize() == 1)
|
|
data = pkt->get<uint8_t>();
|
|
else if (pkt->getSize() == 2)
|
|
data = pkt->get<uint16_t>();
|
|
else
|
|
data = pkt->get<uint32_t>();
|
|
DPRINTF(IdeCtrl, "%s from offset: %#x size: %#x data: %#x\n",
|
|
read ? "Read" : "Write", pkt->getAddr(), pkt->getSize(), data);
|
|
#endif
|
|
|
|
pkt->makeAtomicResponse();
|
|
}
|
|
|
|
Tick
|
|
IdeController::read(PacketPtr pkt)
|
|
{
|
|
dispatchAccess(pkt, true);
|
|
return pioDelay;
|
|
}
|
|
|
|
Tick
|
|
IdeController::write(PacketPtr pkt)
|
|
{
|
|
dispatchAccess(pkt, false);
|
|
return pioDelay;
|
|
}
|
|
|
|
void
|
|
IdeController::serialize(std::ostream &os)
|
|
{
|
|
// Serialize the PciDevice base class
|
|
PciDevice::serialize(os);
|
|
|
|
// Serialize channels
|
|
primary.serialize("primary", os);
|
|
secondary.serialize("secondary", os);
|
|
|
|
// Serialize config registers
|
|
SERIALIZE_SCALAR(primaryTiming);
|
|
SERIALIZE_SCALAR(secondaryTiming);
|
|
SERIALIZE_SCALAR(deviceTiming);
|
|
SERIALIZE_SCALAR(udmaControl);
|
|
SERIALIZE_SCALAR(udmaTiming);
|
|
SERIALIZE_SCALAR(ideConfig);
|
|
|
|
// Serialize internal state
|
|
SERIALIZE_SCALAR(ioEnabled);
|
|
SERIALIZE_SCALAR(bmEnabled);
|
|
SERIALIZE_SCALAR(bmiAddr);
|
|
SERIALIZE_SCALAR(bmiSize);
|
|
}
|
|
|
|
void
|
|
IdeController::Channel::serialize(const std::string &base, std::ostream &os)
|
|
{
|
|
paramOut(os, base + ".cmdAddr", cmdAddr);
|
|
paramOut(os, base + ".cmdSize", cmdSize);
|
|
paramOut(os, base + ".ctrlAddr", ctrlAddr);
|
|
paramOut(os, base + ".ctrlSize", ctrlSize);
|
|
uint8_t command = bmiRegs.command;
|
|
paramOut(os, base + ".bmiRegs.command", command);
|
|
paramOut(os, base + ".bmiRegs.reserved0", bmiRegs.reserved0);
|
|
uint8_t status = bmiRegs.status;
|
|
paramOut(os, base + ".bmiRegs.status", status);
|
|
paramOut(os, base + ".bmiRegs.reserved1", bmiRegs.reserved1);
|
|
paramOut(os, base + ".bmiRegs.bmidtp", bmiRegs.bmidtp);
|
|
paramOut(os, base + ".selectBit", selectBit);
|
|
}
|
|
|
|
void
|
|
IdeController::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
// Unserialize the PciDevice base class
|
|
PciDevice::unserialize(cp, section);
|
|
|
|
// Unserialize channels
|
|
primary.unserialize("primary", cp, section);
|
|
secondary.unserialize("secondary", cp, section);
|
|
|
|
// Unserialize config registers
|
|
UNSERIALIZE_SCALAR(primaryTiming);
|
|
UNSERIALIZE_SCALAR(secondaryTiming);
|
|
UNSERIALIZE_SCALAR(deviceTiming);
|
|
UNSERIALIZE_SCALAR(udmaControl);
|
|
UNSERIALIZE_SCALAR(udmaTiming);
|
|
UNSERIALIZE_SCALAR(ideConfig);
|
|
|
|
// Unserialize internal state
|
|
UNSERIALIZE_SCALAR(ioEnabled);
|
|
UNSERIALIZE_SCALAR(bmEnabled);
|
|
UNSERIALIZE_SCALAR(bmiAddr);
|
|
UNSERIALIZE_SCALAR(bmiSize);
|
|
}
|
|
|
|
void
|
|
IdeController::Channel::unserialize(const std::string &base, Checkpoint *cp,
|
|
const std::string §ion)
|
|
{
|
|
paramIn(cp, section, base + ".cmdAddr", cmdAddr);
|
|
paramIn(cp, section, base + ".cmdSize", cmdSize);
|
|
paramIn(cp, section, base + ".ctrlAddr", ctrlAddr);
|
|
paramIn(cp, section, base + ".ctrlSize", ctrlSize);
|
|
uint8_t command;
|
|
paramIn(cp, section, base +".bmiRegs.command", command);
|
|
bmiRegs.command = command;
|
|
paramIn(cp, section, base + ".bmiRegs.reserved0", bmiRegs.reserved0);
|
|
uint8_t status;
|
|
paramIn(cp, section, base + ".bmiRegs.status", status);
|
|
bmiRegs.status = status;
|
|
paramIn(cp, section, base + ".bmiRegs.reserved1", bmiRegs.reserved1);
|
|
paramIn(cp, section, base + ".bmiRegs.bmidtp", bmiRegs.bmidtp);
|
|
paramIn(cp, section, base + ".selectBit", selectBit);
|
|
select(selectBit);
|
|
}
|
|
|
|
IdeController *
|
|
IdeControllerParams::create()
|
|
{
|
|
return new IdeController(this);
|
|
}
|