25ffa8eb8b
This is to help tidy up arch/x86. These files should not be used external to the ISA. --HG-- rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh
92 lines
3.6 KiB
C++
92 lines
3.6 KiB
C++
/*
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* Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_MMAPEDIPR_HH__
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#define __ARCH_X86_MMAPEDIPR_HH__
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/**
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* @file
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*
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* ISA-specific helper functions for memory mapped IPR accesses.
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*/
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#include "arch/x86/regs/misc.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "mem/packet.hh"
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namespace X86ISA
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{
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inline Tick
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handleIprRead(ThreadContext *xc, Packet *pkt)
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{
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#if !FULL_SYSTEM
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panic("Shouldn't have a memory mapped register in SE\n");
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#else
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Addr offset = pkt->getAddr() & mask(3);
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MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
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MiscReg data = htog(xc->readMiscReg(index));
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// Make sure we don't trot off the end of data.
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assert(offset + pkt->getSize() <= sizeof(MiscReg));
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pkt->setData(((uint8_t *)&data) + offset);
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#endif
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return xc->getCpuPtr()->ticks(1);
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}
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inline Tick
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handleIprWrite(ThreadContext *xc, Packet *pkt)
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{
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#if !FULL_SYSTEM
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panic("Shouldn't have a memory mapped register in SE\n");
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#else
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Addr offset = pkt->getAddr() & mask(3);
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MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
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MiscReg data;
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data = htog(xc->readMiscRegNoEffect(index));
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// Make sure we don't trot off the end of data.
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assert(offset + pkt->getSize() <= sizeof(MiscReg));
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pkt->writeData(((uint8_t *)&data) + offset);
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xc->setMiscReg(index, gtoh(data));
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#endif
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return xc->getCpuPtr()->ticks(1);
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}
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};
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#endif // __ARCH_X86_MMAPEDIPR_HH__
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