This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
718 lines
17 KiB
INI
718 lines
17 KiB
INI
[root]
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type=Root
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children=system
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eventq_index=0
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full_system=false
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sim_quantum=0
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
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boot_osflags=a
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cache_line_size=64
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clk_domain=system.clk_domain
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eventq_index=0
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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load_offset=0
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mem_mode=timing
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mem_ranges=
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memories=system.physmem
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num_work_ids=16
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readfile=
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[0]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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eventq_index=0
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voltage_domain=system.voltage_domain
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[system.cpu]
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type=MinorCPU
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children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
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branchPred=system.cpu.branchPred
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checker=Null
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clk_domain=system.cpu_clk_domain
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cpu_id=0
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decodeCycleInput=true
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decodeInputBufferSize=3
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decodeInputWidth=2
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decodeToExecuteForwardDelay=1
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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dtb=system.cpu.dtb
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enableIdling=true
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eventq_index=0
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executeAllowEarlyMemoryIssue=true
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executeBranchDelay=1
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executeCommitLimit=2
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executeCycleInput=true
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executeFuncUnits=system.cpu.executeFuncUnits
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executeInputBufferSize=7
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executeInputWidth=2
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executeIssueLimit=2
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executeLSQMaxStoreBufferStoresPerCycle=2
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executeLSQRequestsQueueSize=1
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executeLSQStoreBufferSize=5
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executeLSQTransfersQueueSize=2
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executeMaxAccessesInMemory=2
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executeMemoryCommitLimit=1
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executeMemoryIssueLimit=1
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executeMemoryWidth=0
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executeSetTraceTimeOnCommit=true
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executeSetTraceTimeOnIssue=false
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fetch1FetchLimit=1
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fetch1LineSnapWidth=0
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fetch1LineWidth=0
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fetch1ToFetch2BackwardDelay=1
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fetch1ToFetch2ForwardDelay=1
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fetch2CycleInput=true
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fetch2InputBufferSize=2
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fetch2ToDecodeForwardDelay=1
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function_trace=false
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function_trace_start=0
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interrupts=system.cpu.interrupts
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isa=system.cpu.isa
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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profile=0
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progress_interval=0
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simpoint_start_insts=
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switched_out=false
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system=system
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tracer=system.cpu.tracer
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workload=system.cpu.workload
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dcache_port=system.cpu.dcache.cpu_side
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icache_port=system.cpu.icache.cpu_side
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[system.cpu.branchPred]
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type=BranchPredictor
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BTBEntries=4096
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BTBTagSize=16
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RASSize=16
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choiceCtrBits=2
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choicePredictorSize=8192
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eventq_index=0
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globalCtrBits=2
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globalPredictorSize=8192
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instShiftAmt=2
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localCtrBits=2
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localHistoryTableSize=2048
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localPredictorSize=2048
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numThreads=1
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predType=tournament
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[system.cpu.dcache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=262144
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system=system
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tags=system.cpu.dcache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.dcache_port
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mem_side=system.cpu.toL2Bus.slave[1]
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[system.cpu.dcache.tags]
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type=LRU
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assoc=2
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=262144
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[system.cpu.dtb]
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type=AlphaTLB
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eventq_index=0
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size=64
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[system.cpu.executeFuncUnits]
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type=MinorFUPool
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children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
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eventq_index=0
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funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
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[system.cpu.executeFuncUnits.funcUnits0]
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type=MinorFU
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children=opClasses timings
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eventq_index=0
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issueLat=1
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opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
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opLat=3
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timings=system.cpu.executeFuncUnits.funcUnits0.timings
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[system.cpu.executeFuncUnits.funcUnits0.opClasses]
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type=MinorOpClassSet
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children=opClasses
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eventq_index=0
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opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
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[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
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type=MinorOpClass
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eventq_index=0
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opClass=IntAlu
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[system.cpu.executeFuncUnits.funcUnits0.timings]
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type=MinorFUTiming
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children=opClasses
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description=Int
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eventq_index=0
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extraAssumedLat=0
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extraCommitLat=0
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extraCommitLatExpr=Null
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mask=0
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match=0
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opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
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srcRegsRelativeLats=2
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suppress=false
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[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
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type=MinorOpClassSet
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eventq_index=0
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opClasses=
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[system.cpu.executeFuncUnits.funcUnits1]
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type=MinorFU
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children=opClasses timings
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eventq_index=0
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issueLat=1
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opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
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opLat=3
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timings=system.cpu.executeFuncUnits.funcUnits1.timings
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[system.cpu.executeFuncUnits.funcUnits1.opClasses]
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type=MinorOpClassSet
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children=opClasses
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eventq_index=0
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opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
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[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
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type=MinorOpClass
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eventq_index=0
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opClass=IntAlu
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[system.cpu.executeFuncUnits.funcUnits1.timings]
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type=MinorFUTiming
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children=opClasses
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description=Int
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eventq_index=0
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extraAssumedLat=0
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extraCommitLat=0
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extraCommitLatExpr=Null
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mask=0
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match=0
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opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
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srcRegsRelativeLats=2
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suppress=false
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[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
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type=MinorOpClassSet
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eventq_index=0
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opClasses=
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[system.cpu.executeFuncUnits.funcUnits2]
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type=MinorFU
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children=opClasses timings
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eventq_index=0
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issueLat=1
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opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
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opLat=3
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timings=system.cpu.executeFuncUnits.funcUnits2.timings
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[system.cpu.executeFuncUnits.funcUnits2.opClasses]
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type=MinorOpClassSet
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children=opClasses
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eventq_index=0
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opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
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[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
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type=MinorOpClass
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eventq_index=0
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opClass=IntMult
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[system.cpu.executeFuncUnits.funcUnits2.timings]
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type=MinorFUTiming
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children=opClasses
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description=Mul
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eventq_index=0
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extraAssumedLat=0
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extraCommitLat=0
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extraCommitLatExpr=Null
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mask=0
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match=0
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opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
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srcRegsRelativeLats=0
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suppress=false
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[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
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type=MinorOpClassSet
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eventq_index=0
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opClasses=
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[system.cpu.executeFuncUnits.funcUnits3]
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type=MinorFU
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children=opClasses
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eventq_index=0
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issueLat=9
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opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
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opLat=9
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timings=
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[system.cpu.executeFuncUnits.funcUnits3.opClasses]
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type=MinorOpClassSet
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children=opClasses
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eventq_index=0
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opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
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[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
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type=MinorOpClass
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eventq_index=0
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opClass=IntDiv
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[system.cpu.executeFuncUnits.funcUnits4]
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type=MinorFU
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children=opClasses timings
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eventq_index=0
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issueLat=1
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opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
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opLat=6
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timings=system.cpu.executeFuncUnits.funcUnits4.timings
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[system.cpu.executeFuncUnits.funcUnits4.opClasses]
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type=MinorOpClassSet
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children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
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eventq_index=0
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opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
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type=MinorOpClass
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eventq_index=0
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opClass=FloatAdd
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
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type=MinorOpClass
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eventq_index=0
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opClass=FloatCmp
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
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type=MinorOpClass
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eventq_index=0
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opClass=FloatCvt
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
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type=MinorOpClass
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eventq_index=0
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opClass=FloatMult
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
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type=MinorOpClass
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eventq_index=0
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opClass=FloatDiv
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
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type=MinorOpClass
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eventq_index=0
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opClass=FloatSqrt
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
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type=MinorOpClass
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eventq_index=0
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opClass=SimdAdd
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
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type=MinorOpClass
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eventq_index=0
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opClass=SimdAddAcc
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
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type=MinorOpClass
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eventq_index=0
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opClass=SimdAlu
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
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type=MinorOpClass
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eventq_index=0
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opClass=SimdCmp
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
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type=MinorOpClass
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eventq_index=0
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opClass=SimdCvt
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
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type=MinorOpClass
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eventq_index=0
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opClass=SimdMisc
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
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type=MinorOpClass
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eventq_index=0
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opClass=SimdMult
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|
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
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type=MinorOpClass
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eventq_index=0
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opClass=SimdMultAcc
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|
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
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type=MinorOpClass
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eventq_index=0
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opClass=SimdShift
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|
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
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type=MinorOpClass
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eventq_index=0
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opClass=SimdShiftAcc
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|
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
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type=MinorOpClass
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|
eventq_index=0
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opClass=SimdSqrt
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|
|
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[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
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type=MinorOpClass
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|
eventq_index=0
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opClass=SimdFloatAdd
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|
|
|
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
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type=MinorOpClass
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|
eventq_index=0
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opClass=SimdFloatAlu
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|
|
|
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
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|
type=MinorOpClass
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|
eventq_index=0
|
|
opClass=SimdFloatCmp
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|
|
|
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
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|
type=MinorOpClass
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|
eventq_index=0
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|
opClass=SimdFloatCvt
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|
|
|
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
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|
type=MinorOpClass
|
|
eventq_index=0
|
|
opClass=SimdFloatDiv
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|
|
|
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
|
|
type=MinorOpClass
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|
eventq_index=0
|
|
opClass=SimdFloatMisc
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|
|
|
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
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|
type=MinorOpClass
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|
eventq_index=0
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|
opClass=SimdFloatMult
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|
|
|
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
|
|
type=MinorOpClass
|
|
eventq_index=0
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|
opClass=SimdFloatMultAcc
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|
|
|
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
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type=MinorOpClass
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|
eventq_index=0
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opClass=SimdFloatSqrt
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|
|
|
[system.cpu.executeFuncUnits.funcUnits4.timings]
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type=MinorFUTiming
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children=opClasses
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description=FloatSimd
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|
eventq_index=0
|
|
extraAssumedLat=0
|
|
extraCommitLat=0
|
|
extraCommitLatExpr=Null
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|
mask=0
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|
match=0
|
|
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
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|
srcRegsRelativeLats=2
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|
suppress=false
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|
|
|
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
|
|
type=MinorOpClassSet
|
|
eventq_index=0
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|
opClasses=
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|
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[system.cpu.executeFuncUnits.funcUnits5]
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|
type=MinorFU
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|
children=opClasses timings
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|
eventq_index=0
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|
issueLat=1
|
|
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
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|
opLat=1
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|
timings=system.cpu.executeFuncUnits.funcUnits5.timings
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|
|
|
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
|
|
type=MinorOpClassSet
|
|
children=opClasses0 opClasses1
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|
eventq_index=0
|
|
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
|
|
|
|
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
|
|
type=MinorOpClass
|
|
eventq_index=0
|
|
opClass=MemRead
|
|
|
|
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
|
|
type=MinorOpClass
|
|
eventq_index=0
|
|
opClass=MemWrite
|
|
|
|
[system.cpu.executeFuncUnits.funcUnits5.timings]
|
|
type=MinorFUTiming
|
|
children=opClasses
|
|
description=Mem
|
|
eventq_index=0
|
|
extraAssumedLat=2
|
|
extraCommitLat=0
|
|
extraCommitLatExpr=Null
|
|
mask=0
|
|
match=0
|
|
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
|
|
srcRegsRelativeLats=1
|
|
suppress=false
|
|
|
|
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
|
|
type=MinorOpClassSet
|
|
eventq_index=0
|
|
opClasses=
|
|
|
|
[system.cpu.executeFuncUnits.funcUnits6]
|
|
type=MinorFU
|
|
children=opClasses
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
|
|
opLat=1
|
|
timings=
|
|
|
|
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
|
|
type=MinorOpClassSet
|
|
children=opClasses0 opClasses1
|
|
eventq_index=0
|
|
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
|
|
|
|
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
|
|
type=MinorOpClass
|
|
eventq_index=0
|
|
opClass=IprAccess
|
|
|
|
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
|
|
type=MinorOpClass
|
|
eventq_index=0
|
|
opClass=InstPrefetch
|
|
|
|
[system.cpu.icache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=2
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
forward_snoops=true
|
|
hit_latency=2
|
|
is_top_level=true
|
|
max_miss_count=0
|
|
mshrs=4
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=2
|
|
sequential_access=false
|
|
size=131072
|
|
system=system
|
|
tags=system.cpu.icache.tags
|
|
tgts_per_mshr=20
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.icache_port
|
|
mem_side=system.cpu.toL2Bus.slave[0]
|
|
|
|
[system.cpu.icache.tags]
|
|
type=LRU
|
|
assoc=2
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
hit_latency=2
|
|
sequential_access=false
|
|
size=131072
|
|
|
|
[system.cpu.interrupts]
|
|
type=AlphaInterrupts
|
|
eventq_index=0
|
|
|
|
[system.cpu.isa]
|
|
type=AlphaISA
|
|
eventq_index=0
|
|
system=system
|
|
|
|
[system.cpu.itb]
|
|
type=AlphaTLB
|
|
eventq_index=0
|
|
size=48
|
|
|
|
[system.cpu.l2cache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=8
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
forward_snoops=true
|
|
hit_latency=20
|
|
is_top_level=false
|
|
max_miss_count=0
|
|
mshrs=20
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=20
|
|
sequential_access=false
|
|
size=2097152
|
|
system=system
|
|
tags=system.cpu.l2cache.tags
|
|
tgts_per_mshr=12
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.toL2Bus.master[0]
|
|
mem_side=system.membus.slave[1]
|
|
|
|
[system.cpu.l2cache.tags]
|
|
type=LRU
|
|
assoc=8
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
hit_latency=20
|
|
sequential_access=false
|
|
size=2097152
|
|
|
|
[system.cpu.toL2Bus]
|
|
type=CoherentBus
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=32
|
|
master=system.cpu.l2cache.cpu_side
|
|
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|
|
|
[system.cpu.tracer]
|
|
type=ExeTracer
|
|
eventq_index=0
|
|
|
|
[system.cpu.workload]
|
|
type=LiveProcess
|
|
cmd=hello
|
|
cwd=
|
|
egid=100
|
|
env=
|
|
errout=cerr
|
|
euid=100
|
|
eventq_index=0
|
|
executable=/arm/projectscratch/pd/sysrandd/dist/test-progs/hello/bin/alpha/linux/hello
|
|
gid=100
|
|
input=cin
|
|
max_stack_size=67108864
|
|
output=cout
|
|
pid=100
|
|
ppid=99
|
|
simpoint=0
|
|
system=system
|
|
uid=100
|
|
|
|
[system.cpu_clk_domain]
|
|
type=SrcClockDomain
|
|
clock=500
|
|
eventq_index=0
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.membus]
|
|
type=CoherentBus
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=8
|
|
master=system.physmem.port
|
|
slave=system.system_port system.cpu.l2cache.mem_side
|
|
|
|
[system.physmem]
|
|
type=DRAMCtrl
|
|
activation_limit=4
|
|
addr_mapping=RoRaBaChCo
|
|
banks_per_rank=8
|
|
burst_length=8
|
|
channels=1
|
|
clk_domain=system.clk_domain
|
|
conf_table_reported=true
|
|
device_bus_width=8
|
|
device_rowbuffer_size=1024
|
|
devices_per_rank=8
|
|
eventq_index=0
|
|
in_addr_map=true
|
|
max_accesses_per_row=16
|
|
mem_sched_policy=frfcfs
|
|
min_writes_per_switch=16
|
|
null=false
|
|
page_policy=open_adaptive
|
|
range=0:134217727
|
|
ranks_per_channel=2
|
|
read_buffer_size=32
|
|
static_backend_latency=10000
|
|
static_frontend_latency=10000
|
|
tBURST=5000
|
|
tCL=13750
|
|
tRAS=35000
|
|
tRCD=13750
|
|
tREFI=7800000
|
|
tRFC=300000
|
|
tRP=13750
|
|
tRRD=6250
|
|
tWTR=7500
|
|
tXAW=40000
|
|
write_buffer_size=64
|
|
write_high_thresh_perc=85
|
|
write_low_thresh_perc=50
|
|
port=system.membus.master[0]
|
|
|
|
[system.voltage_domain]
|
|
type=VoltageDomain
|
|
eventq_index=0
|
|
voltage=1.000000
|
|
|