5b08e211ab
Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
1099 lines
125 KiB
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1099 lines
125 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.201640 # Number of seconds simulated
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sim_ticks 201639641000 # Number of ticks simulated
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final_tick 201639641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 135689 # Simulator instruction rate (inst/s)
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host_op_rate 152980 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 54153116 # Simulator tick rate (ticks/s)
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host_mem_usage 265540 # Number of bytes of host memory used
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host_seconds 3723.51 # Real time elapsed on the host
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sim_insts 505237723 # Number of instructions simulated
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sim_ops 569624283 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 217344 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9271296 # Number of bytes read from this memory
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system.physmem.bytes_read::total 9488640 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 217344 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 217344 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 6252864 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6252864 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 3396 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 144864 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 148260 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 97701 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 97701 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1077883 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 45979530 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 47057414 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1077883 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1077883 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 31010093 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 31010093 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 31010093 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1077883 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 45979530 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 78067507 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 148261 # Number of read requests accepted
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system.physmem.writeReqs 97701 # Number of write requests accepted
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system.physmem.readBursts 148261 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 97701 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 9478784 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue
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system.physmem.bytesWritten 6251328 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 9488704 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 6252864 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 8 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 9600 # Per bank write bursts
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system.physmem.perBankRdBursts::1 9245 # Per bank write bursts
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system.physmem.perBankRdBursts::2 9272 # Per bank write bursts
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system.physmem.perBankRdBursts::3 9002 # Per bank write bursts
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system.physmem.perBankRdBursts::4 9776 # Per bank write bursts
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system.physmem.perBankRdBursts::5 9633 # Per bank write bursts
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system.physmem.perBankRdBursts::6 9118 # Per bank write bursts
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system.physmem.perBankRdBursts::7 8324 # Per bank write bursts
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system.physmem.perBankRdBursts::8 8782 # Per bank write bursts
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system.physmem.perBankRdBursts::9 8907 # Per bank write bursts
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system.physmem.perBankRdBursts::10 8927 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9740 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9612 # Per bank write bursts
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system.physmem.perBankRdBursts::13 9774 # Per bank write bursts
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system.physmem.perBankRdBursts::14 8952 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9442 # Per bank write bursts
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system.physmem.perBankWrBursts::0 6262 # Per bank write bursts
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system.physmem.perBankWrBursts::1 6157 # Per bank write bursts
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system.physmem.perBankWrBursts::2 6103 # Per bank write bursts
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system.physmem.perBankWrBursts::3 5900 # Per bank write bursts
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system.physmem.perBankWrBursts::4 6261 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6280 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6052 # Per bank write bursts
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system.physmem.perBankWrBursts::7 5550 # Per bank write bursts
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system.physmem.perBankWrBursts::8 5797 # Per bank write bursts
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system.physmem.perBankWrBursts::9 5910 # Per bank write bursts
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system.physmem.perBankWrBursts::10 5990 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6523 # Per bank write bursts
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system.physmem.perBankWrBursts::12 6359 # Per bank write bursts
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system.physmem.perBankWrBursts::13 6344 # Per bank write bursts
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system.physmem.perBankWrBursts::14 6057 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6132 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 201639615000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 148261 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 97701 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 138302 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 9255 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 486 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2250 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2402 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5790 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5812 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5837 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5837 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 5855 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 5847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5870 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5853 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5913 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 6010 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 5828 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5805 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5732 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 65483 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 240.203045 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 153.557671 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 255.515687 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 26845 41.00% 41.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 17105 26.12% 67.12% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 6057 9.25% 76.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 6227 9.51% 85.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 3215 4.91% 90.79% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1344 2.05% 92.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 866 1.32% 94.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 634 0.97% 95.13% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 3190 4.87% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 65483 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5723 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 25.877861 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 376.772634 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 5719 99.93% 99.93% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 5723 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5723 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.067447 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.968448 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 2.305335 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-17 3462 60.49% 60.49% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18-19 2077 36.29% 96.78% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::20-21 88 1.54% 98.32% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22-23 26 0.45% 98.78% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24-25 19 0.33% 99.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::26-27 9 0.16% 99.27% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-29 14 0.24% 99.51% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::30-31 5 0.09% 99.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-33 2 0.03% 99.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::34-35 1 0.02% 99.65% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::36-37 6 0.10% 99.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::38-39 2 0.03% 99.79% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-41 3 0.05% 99.84% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-45 2 0.03% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::46-47 1 0.02% 99.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-53 2 0.03% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::54-55 2 0.03% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-57 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::total 5723 # Writes before turning the bus around for reads
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|
system.physmem.totQLat 1816896000 # Total ticks spent queuing
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|
system.physmem.totMemAccLat 4593883500 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 740530000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 12267.54 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 31017.54 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 47.01 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 31.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 47.06 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 31.01 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.61 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 19.04 # Average write queue length when enqueuing
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system.physmem.readRowHits 116026 # Number of row buffer hits during reads
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system.physmem.writeRowHits 64266 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 78.34 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 65.78 # Row buffer hit rate for writes
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system.physmem.avgGap 819799.87 # Average gap between requests
|
|
system.physmem.pageHitRate 73.35 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 120286035750 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 6732960000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 74617456750 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.membus.throughput 78067507 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 46965 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 46964 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 97701 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 8 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 101296 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 101296 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394238 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 394238 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15741504 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 15741504 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 15741504 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1079764000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 1396376742 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 185905498 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 145717903 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 7288959 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 95047377 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 88827374 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 93.455892 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 12842646 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 117058 # Number of incorrect RAS predictions.
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 548 # Number of system calls
|
|
system.cpu.numCycles 403279283 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 120682752 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 776131290 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 185905498 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 101670020 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 172998904 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 37503258 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 68039482 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 481 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 115897812 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 2525334 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 391132406 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.225985 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.009732 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 218146201 55.77% 55.77% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 14394493 3.68% 59.45% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 23167694 5.92% 65.38% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 22933314 5.86% 71.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 21066439 5.39% 76.63% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 11728153 3.00% 79.62% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 13552888 3.47% 83.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 12244725 3.13% 86.22% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 53898499 13.78% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 391132406 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.460984 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.924550 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 127941260 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 66012107 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 164309835 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 3533487 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 29335717 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 26533351 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 77647 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 841607037 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 303900 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 29335717 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 132935936 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 7523486 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 48032128 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 162776327 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 10528812 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 816179204 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 4868 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 4457827 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 3314300 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 1212194 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.FullRegisterEvents 4787 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 972434380 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 3587695415 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 3300630013 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 306182089 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 2293511 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 2293509 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 23291983 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 173719051 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 74905434 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 30225729 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 17207987 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 768522572 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 3775769 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 668800812 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 1727981 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 200793138 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 527082191 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 798137 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 391132406 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.709909 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.765965 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 138616997 35.44% 35.44% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 67517265 17.26% 52.70% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 69869307 17.86% 70.57% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 51755005 13.23% 83.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 32440287 8.29% 92.09% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 16135836 4.13% 96.22% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 9617335 2.46% 98.68% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 3307412 0.85% 99.52% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 1872962 0.48% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 391132406 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 630442 6.26% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 6879641 68.30% 74.56% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 2562211 25.44% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 449864838 67.26% 67.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 383889 0.06% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 102 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 154509639 23.10% 90.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 64042341 9.58% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 668800812 # Type of FU issued
|
|
system.cpu.iq.rate 1.658406 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 10072294 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.015060 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 1740534066 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 973902079 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 649227410 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 239 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 322 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 678872985 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 121 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 9444118 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 47689496 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 34046 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 814715 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 18044957 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 19567 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 5233 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 29335717 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 3955691 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1178658 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 773883644 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 1025688 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 173719051 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 74905434 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 2287227 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 242970 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 870100 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 814715 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 4363839 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 4034750 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 8398589 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 659340001 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 151050186 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 9460811 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1585303 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 213740794 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 139088077 # Number of branches executed
|
|
system.cpu.iew.exec_stores 62690608 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.634946 # Inst execution rate
|
|
system.cpu.iew.wb_sent 654323635 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 649227426 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 378014910 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 657704988 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.609871 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.574748 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 202955681 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 7214032 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 361796689 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.578146 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.256071 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 156712744 43.32% 43.32% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 96319147 26.62% 69.94% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 33326252 9.21% 79.15% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 17957546 4.96% 84.11% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 16748053 4.63% 88.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 7262749 2.01% 90.75% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 6923592 1.91% 92.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 3096479 0.86% 93.52% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 23450127 6.48% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 361796689 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
|
|
system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 182890032 # Number of memory references committed
|
|
system.cpu.commit.loads 126029555 # Number of loads committed
|
|
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
|
system.cpu.commit.branches 121548301 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 470727693 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 387738913 67.91% 67.91% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 339219 0.06% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.97% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 126029555 22.07% 90.04% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 56860477 9.96% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 570968167 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 23450127 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 1112263272 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1577313182 # The number of ROB writes
|
|
system.cpu.timesIdled 375340 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 12146877 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
|
|
system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.798197 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.798197 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.252823 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.252823 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 3074448522 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 755651134 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 238959520 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 738060588 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 865494 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 865493 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1111057 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 86 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 86 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 348798 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 348798 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34444 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505273 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 3539717 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1099136 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147717056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 148816192 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 148816192 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 6080 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2273774999 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 26477230 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1825044731 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 15336 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1096.367650 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 115876238 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 17184 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 6743.263385 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1096.367650 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.535336 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.535336 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1848 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.902344 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 231812889 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 231812889 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 115876248 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 115876248 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 115876248 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 115876248 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 115876248 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 115876248 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 21562 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 21562 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 21562 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 21562 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 21562 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 21562 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 560819979 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 560819979 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 560819979 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 560819979 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 560819979 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 560819979 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 115897810 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 115897810 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 115897810 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 115897810 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 115897810 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 115897810 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26009.645627 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 26009.645627 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26009.645627 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 26009.645627 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26009.645627 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 26009.645627 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 1208 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 75.500000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4292 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 4292 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 4292 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 4292 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 4292 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 4292 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17270 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 17270 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 17270 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 17270 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 17270 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 17270 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 408247770 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 408247770 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 408247770 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 408247770 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 408247770 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 408247770 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23639.129705 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23639.129705 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23639.129705 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 23639.129705 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23639.129705 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 23639.129705 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 115515 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 27068.910861 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1781873 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 146764 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 12.141077 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 90165895500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 22998.912938 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 364.941054 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 3705.056868 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.701871 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011137 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.113069 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.826078 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31249 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2187 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7697 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21300 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953644 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 19098361 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 19098361 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 13774 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 804634 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 818408 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1111057 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1111057 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 79 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 79 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 247501 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 247501 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 13774 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1052135 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1065909 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 13774 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1052135 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1065909 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3401 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 43590 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 46991 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 7 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 101297 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 101297 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3401 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 144887 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 148288 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3401 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 144887 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 148288 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 252890250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3330417250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 3583307500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7356301749 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 7356301749 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 252890250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10686718999 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 10939609249 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 252890250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10686718999 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 10939609249 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 17175 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 848224 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 865399 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1111057 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1111057 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 86 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 348798 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 348798 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 17175 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1197022 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1214197 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 17175 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1197022 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1214197 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.198020 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051390 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.054300 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.081395 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.081395 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290417 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.290417 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.198020 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.121040 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.122128 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.198020 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.121040 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.122128 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74357.615407 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76403.240422 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76255.187163 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72621.121544 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72621.121544 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74357.615407 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73758.991483 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 73772.720982 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74357.615407 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73758.991483 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 73772.720982 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 97701 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 97701 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3397 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43568 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 46965 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101297 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 101297 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3397 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 144865 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 148262 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3397 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 144865 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 148262 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 209923500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2783807500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2993731000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 70007 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 70007 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6072932751 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6072932751 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 209923500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8856740251 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9066663751 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 209923500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8856740251 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9066663751 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.197787 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051364 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054270 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.081395 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.081395 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290417 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290417 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.197787 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121021 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.122107 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.197787 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121021 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.122107 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61796.732411 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63895.691792 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63743.873097 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59951.753270 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59951.753270 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61796.732411 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61137.888731 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61152.984251 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61796.732411 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61137.888731 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61152.984251 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1192926 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4057.383105 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 190117545 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1197022 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 158.825439 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 4253859250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4057.383105 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.990572 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.990572 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2354 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1689 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 391573870 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 391573870 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 136255144 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 136255144 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 50884737 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 50884737 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488854 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1488854 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 187139881 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 187139881 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 187139881 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 187139881 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1716538 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1716538 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 3354569 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 3354569 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 5071107 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 5071107 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 5071107 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 5071107 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29658271464 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 29658271464 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 73164049214 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 73164049214 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 726000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 726000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 102822320678 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 102822320678 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 102822320678 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 102822320678 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 137971682 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 137971682 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488895 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488895 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 192210988 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 192210988 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 192210988 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 192210988 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012441 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.012441 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061848 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.061848 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.026383 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.026383 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.026383 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.026383 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17277.957997 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 17277.957997 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21810.268089 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 21810.268089 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17707.317073 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17707.317073 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 20276.109472 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 20276.109472 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 17575 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 53737 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1744 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 663 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.077408 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 81.051282 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1111057 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1111057 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867776 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 867776 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3006223 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3006223 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3873999 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3873999 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3873999 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3873999 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848762 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 848762 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348346 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 348346 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1197108 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1197108 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1197108 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1197108 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264084776 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264084776 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10175822989 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10175822989 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22439907765 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 22439907765 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22439907765 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 22439907765 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14449.380128 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14449.380128 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29211.826715 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29211.826715 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|