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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
Steve Reinhardt 5b08e211ab stats: update for O3 changes 
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM.  At the other extreme, X86 70.twolf is 0.8%
slower.
2014-06-22 14:33:09 -07:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.842688 # Number of seconds simulated
sim_ticks 1842688380000 # Number of ticks simulated
final_tick 1842688380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 219315 # Simulator instruction rate (inst/s)
host_op_rate 219315 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5608158508 # Simulator tick rate (ticks/s)
host_mem_usage 303992 # Number of bytes of host memory used
host_seconds 328.57 # Real time elapsed on the host
sim_insts 72060922 # Number of instructions simulated
sim_ops 72060922 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 480512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 20113024 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 147456 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2236096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 291264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2520128 # Number of bytes read from this memory
system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 480512 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 147456 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 291264 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7466176 # Number of bytes written to this memory
system.physmem.bytes_written::total 7466176 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 7508 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 314266 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2304 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 34939 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 4551 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 39377 # Number of read requests responded to by this memory
system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 116659 # Number of write requests responded to by this memory
system.physmem.num_writes::total 116659 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 260767 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 10915044 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1439393 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 80022 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1213497 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 158065 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 1367637 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15434423 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 260767 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 80022 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 158065 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 498854 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4051784 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4051784 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4051784 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 260767 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 10915044 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1439393 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 80022 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1213497 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 158065 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1367637 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19486207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 98062 # Number of read requests accepted
system.physmem.writeReqs 44473 # Number of write requests accepted
system.physmem.readBursts 98062 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 44473 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 6274816 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue
system.physmem.bytesWritten 2845184 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 6275968 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 2846272 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 6096 # Per bank write bursts
system.physmem.perBankRdBursts::1 5927 # Per bank write bursts
system.physmem.perBankRdBursts::2 6222 # Per bank write bursts
system.physmem.perBankRdBursts::3 6258 # Per bank write bursts
system.physmem.perBankRdBursts::4 5693 # Per bank write bursts
system.physmem.perBankRdBursts::5 6247 # Per bank write bursts
system.physmem.perBankRdBursts::6 5971 # Per bank write bursts
system.physmem.perBankRdBursts::7 5980 # Per bank write bursts
system.physmem.perBankRdBursts::8 6426 # Per bank write bursts
system.physmem.perBankRdBursts::9 5994 # Per bank write bursts
system.physmem.perBankRdBursts::10 6527 # Per bank write bursts
system.physmem.perBankRdBursts::11 6117 # Per bank write bursts
system.physmem.perBankRdBursts::12 5881 # Per bank write bursts
system.physmem.perBankRdBursts::13 6322 # Per bank write bursts
system.physmem.perBankRdBursts::14 6340 # Per bank write bursts
system.physmem.perBankRdBursts::15 6043 # Per bank write bursts
system.physmem.perBankWrBursts::0 2729 # Per bank write bursts
system.physmem.perBankWrBursts::1 2556 # Per bank write bursts
system.physmem.perBankWrBursts::2 2841 # Per bank write bursts
system.physmem.perBankWrBursts::3 3001 # Per bank write bursts
system.physmem.perBankWrBursts::4 2678 # Per bank write bursts
system.physmem.perBankWrBursts::5 2962 # Per bank write bursts
system.physmem.perBankWrBursts::6 2867 # Per bank write bursts
system.physmem.perBankWrBursts::7 2601 # Per bank write bursts
system.physmem.perBankWrBursts::8 3150 # Per bank write bursts
system.physmem.perBankWrBursts::9 2533 # Per bank write bursts
system.physmem.perBankWrBursts::10 3049 # Per bank write bursts
system.physmem.perBankWrBursts::11 2640 # Per bank write bursts
system.physmem.perBankWrBursts::12 2384 # Per bank write bursts
system.physmem.perBankWrBursts::13 2771 # Per bank write bursts
system.physmem.perBankWrBursts::14 2950 # Per bank write bursts
system.physmem.perBankWrBursts::15 2744 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
system.physmem.totGap 1841676054500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 98062 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 44473 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 65686 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 7740 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 8102 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2064 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 855 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1814 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1613 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1627 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1004 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 871 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 858 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 847 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 653 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 645 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 779 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 766 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 872 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 494 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 391 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 362 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 43 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 586 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 612 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 1247 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 1386 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 1579 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 1688 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 1686 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 1737 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1810 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 1870 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 1937 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 2004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 2070 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 2198 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 2105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 2188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 2144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 2115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 355 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 362 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 402 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 456 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 479 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 497 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 562 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 666 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 784 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 853 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 792 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 771 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 700 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 689 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 741 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 691 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 362 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 29 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 21822 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 417.926863 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 236.963090 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 396.574874 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 6839 31.34% 31.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 4667 21.39% 52.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 1650 7.56% 60.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1022 4.68% 64.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 930 4.26% 69.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 496 2.27% 71.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 383 1.76% 73.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 375 1.72% 74.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5460 25.02% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 21822 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 2614 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 37.504973 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 907.786867 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 2612 99.92% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.04% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.04% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 2614 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 2614 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.006886 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.398766 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 4.165807 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1 24 0.92% 0.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2 7 0.27% 1.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3 2 0.08% 1.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4 1 0.04% 1.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5 1 0.04% 1.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::7 3 0.11% 1.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8 2 0.08% 1.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::10 1 0.04% 1.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::13 1 0.04% 1.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::15 1 0.04% 1.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 1860 71.16% 72.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 26 0.99% 73.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 431 16.49% 90.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 74 2.83% 93.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 23 0.88% 93.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 9 0.34% 94.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 11 0.42% 94.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 40 1.53% 96.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 8 0.31% 96.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 18 0.69% 97.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 8 0.31% 97.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 7 0.27% 97.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 3 0.11% 97.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 5 0.19% 98.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 6 0.23% 98.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 9 0.34% 98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32 5 0.19% 98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33 1 0.04% 98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34 1 0.04% 99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35 1 0.04% 99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36 1 0.04% 99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37 1 0.04% 99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39 4 0.15% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41 3 0.11% 99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42 2 0.08% 99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43 1 0.04% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47 1 0.04% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48 4 0.15% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::51 1 0.04% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::53 1 0.04% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56 3 0.11% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::57 2 0.08% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58 1 0.04% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 2614 # Writes before turning the bus around for reads
system.physmem.totQLat 2880597750 # Total ticks spent queuing
system.physmem.totMemAccLat 4718922750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 490220000 # Total ticks spent in databus transfers
system.physmem.avgQLat 29380.66 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 48130.66 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.41 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.41 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing
system.physmem.avgWrQLen 4.05 # Average write queue length when enqueuing
system.physmem.readRowHits 85382 # Number of row buffer hits during reads
system.physmem.writeRowHits 35296 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 79.37 # Row buffer hit rate for writes
system.physmem.avgGap 12920868.94 # Average gap between requests
system.physmem.pageHitRate 84.68 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 1767714784750 # Time in different power states
system.physmem.memoryStateTime::REF 61531340000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 13440274000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 19530148 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 44582 # Transaction distribution
system.membus.trans_dist::ReadResp 44547 # Transaction distribution
system.membus.trans_dist::WriteReq 3734 # Transaction distribution
system.membus.trans_dist::WriteResp 3734 # Transaction distribution
system.membus.trans_dist::Writeback 44473 # Transaction distribution
system.membus.trans_dist::UpgradeReq 43 # Transaction distribution
system.membus.trans_dist::UpgradeResp 43 # Transaction distribution
system.membus.trans_dist::ReadExReq 56556 # Transaction distribution
system.membus.trans_dist::ReadExResp 56556 # Transaction distribution
system.membus.trans_dist::BadAddressError 35 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13238 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 190124 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 70 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 203432 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 254144 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15652 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6962432 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 6978084 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 9137892 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 35977992 # Total data (bytes)
system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 12394500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 511002500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 45000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 763523207 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 153153250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 337462 # number of replacements
system.l2c.tags.tagsinuse 65424.483078 # Cycle average of tags in use
system.l2c.tags.total_refs 2473806 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 402625 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 6.144194 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 54864.362424 # Average occupied blocks per requestor
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system.l2c.tags.occ_blocks::cpu1.inst 576.513665 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 589.890909 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2235.608932 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 2183.164099 # Average occupied blocks per requestor
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system.l2c.tags.occ_percent::cpu0.data 0.040369 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::cpu1.data 0.009001 # Average percentage of cache occupancy
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system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 1028 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 5611 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 55380 # Occupied blocks per task id
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system.l2c.ReadReq_hits::cpu2.data 240703 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1755062 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 835893 # number of Writeback hits
system.l2c.Writeback_hits::total 835893 # number of Writeback hits
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system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits
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system.l2c.UpgradeReq_mshr_miss_latency::total 241006 # number of UpgradeReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1489833024 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 2506807034 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 140206252 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1926569760 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 287277500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 2469072275 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 4823125787 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 140206252 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1926569760 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 287277500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 2469072275 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 4823125787 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 272308500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 292895500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 565204000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 339653500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 403064000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 742717500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 611962000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 695959500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 1307921500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018149 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.167690 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015227 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.069502 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.020379 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.750000 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.375000 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408909 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241029 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.131134 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018149 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.241892 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015227 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.113484 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.034673 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018149 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.241892 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015227 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.113484 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.034673 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60853.407986 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54161.947719 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63124.038673 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54465.723956 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 55643.287042 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 26778.444444 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 26778.444444 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55896.120149 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69294.559256 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 63153.298584 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60853.407986 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55063.729279 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63124.038673 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62541.408724 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59308.991257 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60853.407986 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55063.729279 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63124.038673 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62541.408724 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59308.991257 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.254888 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1694865618000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.254888 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 9303463 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 5047462530 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 5047462530 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 5056765993 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 5056765993 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 5056765993 # number of overall miss cycles
system.iocache.overall_miss_latency::total 5056765993 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 121473.395504 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 121473.395504 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 121192.714032 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 121192.714032 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 121192.714032 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 121192.714032 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 149207 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 11483 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 12.993730 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4167935030 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 4167935030 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 4173649493 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 4173649493 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 4173649493 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 4173649493 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246681.760772 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 246681.760772 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 4913708 # DTB read hits
system.cpu0.dtb.read_misses 6100 # DTB read misses
system.cpu0.dtb.read_acv 126 # DTB read access violations
system.cpu0.dtb.read_accesses 428235 # DTB read accesses
system.cpu0.dtb.write_hits 3510172 # DTB write hits
system.cpu0.dtb.write_misses 671 # DTB write misses
system.cpu0.dtb.write_acv 84 # DTB write access violations
system.cpu0.dtb.write_accesses 163990 # DTB write accesses
system.cpu0.dtb.data_hits 8423880 # DTB hits
system.cpu0.dtb.data_misses 6771 # DTB misses
system.cpu0.dtb.data_acv 210 # DTB access violations
system.cpu0.dtb.data_accesses 592225 # DTB accesses
system.cpu0.itb.fetch_hits 2758823 # ITB hits
system.cpu0.itb.fetch_misses 3034 # ITB misses
system.cpu0.itb.fetch_acv 104 # ITB acv
system.cpu0.itb.fetch_accesses 2761857 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 928196841 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 33463552 # Number of instructions committed
system.cpu0.committedOps 33463552 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 31328637 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 169756 # Number of float alu accesses
system.cpu0.num_func_calls 812549 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4574772 # number of instructions that are conditional controls
system.cpu0.num_int_insts 31328637 # number of integer instructions
system.cpu0.num_fp_insts 169756 # number of float instructions
system.cpu0.num_int_register_reads 43916482 # number of times the integer registers were read
system.cpu0.num_int_register_writes 22873823 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 87693 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 89172 # number of times the floating registers were written
system.cpu0.num_mem_refs 8454037 # number of memory refs
system.cpu0.num_load_insts 4935095 # Number of load instructions
system.cpu0.num_store_insts 3518942 # Number of store instructions
system.cpu0.num_idle_cycles 904607153.884767 # Number of idle cycles
system.cpu0.num_busy_cycles 23589687.115233 # Number of busy cycles
system.cpu0.not_idle_fraction 0.025415 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.974585 # Percentage of idle cycles
system.cpu0.Branches 5650356 # Number of branches fetched
system.cpu0.op_class::No_OpClass 1614853 4.82% 4.82% # Class of executed instruction
system.cpu0.op_class::IntAlu 22689020 67.79% 72.61% # Class of executed instruction
system.cpu0.op_class::IntMult 32419 0.10% 72.71% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 72.71% # Class of executed instruction
system.cpu0.op_class::FloatAdd 12179 0.04% 72.75% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::FloatDiv 1606 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.75% # Class of executed instruction
system.cpu0.op_class::MemRead 5069147 15.15% 87.90% # Class of executed instruction
system.cpu0.op_class::MemWrite 3522084 10.52% 98.42% # Class of executed instruction
system.cpu0.op_class::IprAccess 529225 1.58% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 33470533 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 211388 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 74806 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 73439 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 73439 49.30% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 148960 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1819515986000 98.74% 98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 38828500 0.00% 98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 364353500 0.02% 98.76% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 22768442500 1.24% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1842687610500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.694807 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.815839 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 326 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 192241 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1907
system.cpu0.kern.mode_good::user 1737
system.cpu0.kern.mode_good::idle 170
system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 29751992000 1.61% 1.61% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 2580511000 0.14% 1.75% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 1810355103000 98.25% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 4177 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.throughput 110521342 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 787621 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 787571 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 3734 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 3734 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 372342 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 150591 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 133695 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 35 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 851659 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370714 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 2222373 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27252672 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55368420 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 82621092 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 203645448 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 10944 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 2139903500 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1918103434 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 2234598905 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.iobus.throughput 1469149 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 2954 # Transaction distribution
system.iobus.trans_dist::ReadResp 2954 # Transaction distribution
system.iobus.trans_dist::WriteReq 20630 # Transaction distribution
system.iobus.trans_dist::WriteResp 20630 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2332 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8304 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2378 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 22 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 13238 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 47168 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9328 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1550 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 17 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 15652 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 1098444 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2707184 # Total data (bytes)
system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 6188000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 1792000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 13000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 154562743 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 9504000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 17636750 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.icache.tags.replacements 951958 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.193866 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 42822968 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 952469 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 44.959960 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 10341081250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 254.383910 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 92.394710 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.415245 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.496844 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.180458 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321124 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998426 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 44744661 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 44744661 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 32943729 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 7613321 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2265918 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 42822968 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 32943729 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 7613321 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2265918 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 42822968 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 32943729 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 7613321 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2265918 # number of overall hits
system.cpu0.icache.overall_hits::total 42822968 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 526804 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 126948 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 315301 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 969053 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 526804 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 126948 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 315301 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 969053 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 526804 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 126948 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 315301 # number of overall misses
system.cpu0.icache.overall_misses::total 969053 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1804971752 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4436657422 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6241629174 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1804971752 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4436657422 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6241629174 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1804971752 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4436657422 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6241629174 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 33470533 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 7740269 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 2581219 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 43792021 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 33470533 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 7740269 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 2581219 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 43792021 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 33470533 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 7740269 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 2581219 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 43792021 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015739 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016401 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122152 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.022129 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015739 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016401 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122152 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.022129 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015739 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016401 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122152 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.022129 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14218.197624 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14071.180941 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6440.957485 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14218.197624 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14071.180941 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6440.957485 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14218.197624 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14071.180941 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6440.957485 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 2807 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 180 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 158 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.765823 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 180 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16413 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 16413 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 16413 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 16413 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 16413 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 16413 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126948 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 298888 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 425836 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 126948 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 298888 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 425836 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 126948 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 298888 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 425836 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1550155248 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3653520809 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5203676057 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1550155248 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3653520809 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 5203676057 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1550155248 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3653520809 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 5203676057 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016401 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009724 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016401 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.009724 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016401 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.009724 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12219.906389 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12219.906389 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12219.906389 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 1392214 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 13295925 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1392726 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 9.546691 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.443226 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 126.415700 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.138886 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.496959 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.246906 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.256131 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 63306620 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63306620 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 4076279 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::total 7570448 # number of ReadReq hits
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system.cpu0.dcache.WriteReq_hits::cpu2.data 1295168 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5341772 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117096 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19328 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47935 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 184359 # number of LoadLockedReq hits
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system.cpu0.dcache.StoreCondReq_hits::total 199291 # number of StoreCondReq hits
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system.cpu0.dcache.overall_hits::total 12912220 # number of overall hits
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system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7048 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 18841 # number of LoadLockedReq misses
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system.cpu0.dcache.overall_misses::total 2163760 # number of overall misses
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system.cpu0.dcache.ReadReq_miss_latency::total 11644573250 # number of ReadReq miss cycles
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system.cpu0.dcache.overall_miss_latency::cpu2.data 27444548063 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 31331683823 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 4797880 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1182534 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 2943770 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8924184 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3383049 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 877063 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 1891684 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 6151796 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126730 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21487 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54983 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 203200 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126166 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21357 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51770 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 199293 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8180929 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 2059597 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 4835454 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 15075980 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 8180929 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 2059597 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 4835454 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 15075980 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150400 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082864 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181449 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.151693 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049959 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050732 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315336 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.131673 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076020 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100479 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.128185 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092721 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000010 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108865 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069181 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233827 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.143524 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108865 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069181 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233827 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.143524 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22820.183182 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17613.987775 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 8601.805116 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37104.978312 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30235.776682 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 24304.354652 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13189.439555 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16369.395431 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7634.812324 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6500 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27281.017370 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24273.012037 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14480.202898 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27281.017370 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24273.012037 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14480.202898 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 642685 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 913 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 30067 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.375096 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 130.428571 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 835893 # number of writebacks
system.cpu0.dcache.writebacks::total 835893 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280644 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 280644 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507552 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 507552 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1619 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1619 # number of LoadLockedReq MSHR hits
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system.cpu0.dcache.demand_mshr_hits::total 788196 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 788196 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 788196 # number of overall MSHR hits
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system.cpu0.dcache.ReadReq_mshr_misses::total 351491 # number of ReadReq MSHR misses
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system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5429 # number of LoadLockedReq MSHR misses
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system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2601199489 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6854038231 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 10440391471 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3586353240 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6854038231 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10440391471 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 290678000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 312039500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 602717500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 359850500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 427676500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 787527000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 650528500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 739716000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1390244500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082864 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086114 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039386 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050732 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047029 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021694 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100479 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098740 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037343 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.032167 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.032167 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20743.108991 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16776.418010 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17882.267233 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34919.339027 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29238.787476 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31132.673548 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11188.513201 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12190.504881 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.409989 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 1201953 # DTB read hits
system.cpu1.dtb.read_misses 1367 # DTB read misses
system.cpu1.dtb.read_acv 34 # DTB read access violations
system.cpu1.dtb.read_accesses 142945 # DTB read accesses
system.cpu1.dtb.write_hits 898873 # DTB write hits
system.cpu1.dtb.write_misses 185 # DTB write misses
system.cpu1.dtb.write_acv 23 # DTB write access violations
system.cpu1.dtb.write_accesses 58321 # DTB write accesses
system.cpu1.dtb.data_hits 2100826 # DTB hits
system.cpu1.dtb.data_misses 1552 # DTB misses
system.cpu1.dtb.data_acv 57 # DTB access violations
system.cpu1.dtb.data_accesses 201266 # DTB accesses
system.cpu1.itb.fetch_hits 861128 # ITB hits
system.cpu1.itb.fetch_misses 693 # ITB misses
system.cpu1.itb.fetch_acv 30 # ITB acv
system.cpu1.itb.fetch_accesses 861821 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 953604102 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 7738659 # Number of instructions committed
system.cpu1.committedOps 7738659 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 7195320 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 44971 # Number of float alu accesses
system.cpu1.num_func_calls 212104 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 948894 # number of instructions that are conditional controls
system.cpu1.num_int_insts 7195320 # number of integer instructions
system.cpu1.num_fp_insts 44971 # number of float instructions
system.cpu1.num_int_register_reads 10028277 # number of times the integer registers were read
system.cpu1.num_int_register_writes 5244710 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 24303 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 24579 # number of times the floating registers were written
system.cpu1.num_mem_refs 2108049 # number of memory refs
system.cpu1.num_load_insts 1206835 # Number of load instructions
system.cpu1.num_store_insts 901214 # Number of store instructions
system.cpu1.num_idle_cycles 922268722.786044 # Number of idle cycles
system.cpu1.num_busy_cycles 31335379.213956 # Number of busy cycles
system.cpu1.not_idle_fraction 0.032860 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.967140 # Percentage of idle cycles
system.cpu1.Branches 1227675 # Number of branches fetched
system.cpu1.op_class::No_OpClass 413043 5.34% 5.34% # Class of executed instruction
system.cpu1.op_class::IntAlu 5041451 65.13% 70.47% # Class of executed instruction
system.cpu1.op_class::IntMult 8548 0.11% 70.58% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 70.58% # Class of executed instruction
system.cpu1.op_class::FloatAdd 4999 0.06% 70.64% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 70.64% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 70.64% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 70.64% # Class of executed instruction
system.cpu1.op_class::FloatDiv 810 0.01% 70.65% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.65% # Class of executed instruction
system.cpu1.op_class::MemRead 1235944 15.97% 86.62% # Class of executed instruction
system.cpu1.op_class::MemWrite 902434 11.66% 98.28% # Class of executed instruction
system.cpu1.op_class::IprAccess 133039 1.72% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 7740268 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu1.kern.mode_switch::user 0 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 0
system.cpu1.kern.mode_good::user 0
system.cpu1.kern.mode_good::idle 0
system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
system.cpu2.branchPred.lookups 8997141 # Number of BP lookups
system.cpu2.branchPred.condPredicted 8310458 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 125233 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 7551874 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 6369180 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 84.339066 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 284910 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 13175 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
system.cpu2.dtb.read_hits 3232647 # DTB read hits
system.cpu2.dtb.read_misses 11674 # DTB read misses
system.cpu2.dtb.read_acv 117 # DTB read access violations
system.cpu2.dtb.read_accesses 217551 # DTB read accesses
system.cpu2.dtb.write_hits 2020818 # DTB write hits
system.cpu2.dtb.write_misses 2669 # DTB write misses
system.cpu2.dtb.write_acv 109 # DTB write access violations
system.cpu2.dtb.write_accesses 82591 # DTB write accesses
system.cpu2.dtb.data_hits 5253465 # DTB hits
system.cpu2.dtb.data_misses 14343 # DTB misses
system.cpu2.dtb.data_acv 226 # DTB access violations
system.cpu2.dtb.data_accesses 300142 # DTB accesses
system.cpu2.itb.fetch_hits 371576 # ITB hits
system.cpu2.itb.fetch_misses 5695 # ITB misses
system.cpu2.itb.fetch_acv 235 # ITB acv
system.cpu2.itb.fetch_accesses 377271 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.write_acv 0 # DTB write access violations
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.numCycles 31002313 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 8393929 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 36824229 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 8997141 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 6654090 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 8723757 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 635832 # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles 9323842 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 10747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 1941 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 64126 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 88179 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 2581223 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 87099 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 27026118 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.362542 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.315525 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 18302361 67.72% 67.72% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 270640 1.00% 68.72% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 435105 1.61% 70.33% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 4809867 17.80% 88.13% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 769933 2.85% 90.98% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 167503 0.62% 91.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 192346 0.71% 92.31% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 444449 1.64% 93.95% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 1633914 6.05% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 27026118 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.290209 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.187790 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 8441173 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 9512814 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 8253964 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 165145 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 407122 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 167309 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 12818 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 36409694 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 40311 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 407122 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 8734574 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 2556870 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 5774789 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 8067686 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 1239186 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 35224318 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 3572 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 388506 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 20310 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 316059 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 23620864 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 44017646 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 43961139 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 52746 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 21667069 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 1953795 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 502665 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 59694 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 2961257 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 3405802 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 2124807 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 397929 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 274147 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 32669106 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 622861 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 32140552 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 36002 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 2321360 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 1217953 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 439629 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 27026118 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.189240 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.607686 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 15119064 55.94% 55.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 2962463 10.96% 66.90% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 1396485 5.17% 72.07% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 5591038 20.69% 92.76% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 885243 3.28% 96.03% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 550698 2.04% 98.07% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 348435 1.29% 99.36% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 154603 0.57% 99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 18089 0.07% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 27026118 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 38019 14.73% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 14.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 117677 45.59% 60.31% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 102444 39.69% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 26413495 82.18% 82.19% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 20160 0.06% 82.25% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.25% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 8429 0.03% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.28% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 3362943 10.46% 92.74% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 2042777 6.36% 99.10% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 289088 0.90% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 32140552 # Type of FU issued
system.cpu2.iq.rate 1.036715 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 258140 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.008032 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 91366801 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 35502508 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 31706710 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 234563 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 114868 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 110893 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 32274032 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 122220 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 191624 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 457264 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 1199 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 4154 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 177923 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 4195 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 54966 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 407122 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 1875775 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 219548 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 34577439 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 209711 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 3405802 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 2124807 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 553318 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 48768 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 120434 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 4154 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 65270 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 127814 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 193084 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 31975437 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 3252613 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 165115 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 1285472 # number of nop insts executed
system.cpu2.iew.exec_refs 5280547 # number of memory reference insts executed
system.cpu2.iew.exec_branches 7393667 # Number of branches executed
system.cpu2.iew.exec_stores 2027934 # Number of stores executed
system.cpu2.iew.exec_rate 1.031389 # Inst execution rate
system.cpu2.iew.wb_sent 31851458 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 31817603 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 18729651 # num instructions producing a value
system.cpu2.iew.wb_consumers 22311181 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.026298 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.839474 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 2502130 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 183232 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 177866 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 26618996 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.203206 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.875540 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 16042703 60.27% 60.27% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 2256116 8.48% 68.74% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1167560 4.39% 73.13% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 5327635 20.01% 93.14% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 518833 1.95% 95.09% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 187130 0.70% 95.80% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 168998 0.63% 96.43% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 171142 0.64% 97.07% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 778879 2.93% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 26618996 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 32028137 # Number of instructions committed
system.cpu2.commit.committedOps 32028137 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 4895422 # Number of memory references committed
system.cpu2.commit.loads 2948538 # Number of loads committed
system.cpu2.commit.membars 64184 # Number of memory barriers committed
system.cpu2.commit.branches 7237241 # Number of branches committed
system.cpu2.commit.fp_insts 109664 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 30577389 # Number of committed integer instructions.
system.cpu2.commit.function_calls 229570 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 1171866 3.66% 3.66% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 25576585 79.86% 83.52% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 19753 0.06% 83.58% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.58% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 8429 0.03% 83.60% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.60% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.60% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.60% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.61% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 3012722 9.41% 93.01% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 1948474 6.08% 99.10% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 289088 0.90% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 32028137 # Class of committed instruction
system.cpu2.commit.bw_lim_events 778879 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 60296509 # The number of ROB reads
system.cpu2.rob.rob_writes 69467378 # The number of ROB writes
system.cpu2.timesIdled 246541 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 3976195 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 1746763449 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 30858711 # Number of Instructions Simulated
system.cpu2.committedOps 30858711 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.004654 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.004654 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.995368 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.995368 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 42053824 # number of integer regfile reads
system.cpu2.int_regfile_writes 22390255 # number of integer regfile writes
system.cpu2.fp_regfile_reads 67731 # number of floating regfile reads
system.cpu2.fp_regfile_writes 68085 # number of floating regfile writes
system.cpu2.misc_regfile_reads 5172203 # number of misc regfile reads
system.cpu2.misc_regfile_writes 258202 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu2.kern.mode_switch::user 0 # number of protection mode switches
system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu2.kern.mode_good::kernel 0
system.cpu2.kern.mode_good::user 0
system.cpu2.kern.mode_good::idle 0
system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu2.kern.swap_context 0 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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